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intel_adsp: make shim header soc specific

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using once single header to support multiple socs and product
generations is error prone and not easily maintained.

Over time we have been adding conditional code in headers and extending
structs  to support new HW features which becomes a problem.

Goal is to keep platform headers in sync with hardware specification and
allow of introduction of new platforms and hardware features by just
introducing a new SoC with its own set of headers.

This is now just a copy of existing cavs-shim.h with slight changes,
goal is to clean this up long term and sync with hardware datasheets and
align on naming as well.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This commit is contained in:
Anas Nashif 2022-07-14 08:02:57 -04:00
commit 423264b96b
16 changed files with 615 additions and 11 deletions
Download patch file Download diff file Expand all files Collapse all files

2
drivers/ipm/ipm_cavs_host.c
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@ -4,7 +4,7 @@
#include <zephyr/kernel.h> #include <zephyr/kernel.h>
#include <zephyr/drivers/ipm.h> #include <zephyr/drivers/ipm.h>
#include <cavs-mem.h> #include <cavs-mem.h>
#include <cavs-shim.h> #include <adsp_shim.h>
#include <cavs_ipc.h> #include <cavs_ipc.h>
/* Matches SOF_IPC_MSG_MAX_SIZE, though in practice nothing anywhere /* Matches SOF_IPC_MSG_MAX_SIZE, though in practice nothing anywhere

2
drivers/timer/intel_adsp_timer.c
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@ -10,7 +10,7 @@
#include <zephyr/drivers/interrupt_controller/dw_ace_v1x.h> #include <zephyr/drivers/interrupt_controller/dw_ace_v1x.h>
#include <cavs-idc.h> #include <cavs-idc.h>
#include <cavs-shim.h> #include <adsp_shim.h>
#ifdef CONFIG_SOC_SERIES_INTEL_ACE1X #ifdef CONFIG_SOC_SERIES_INTEL_ACE1X
#include <ace_v1x-regs.h> #include <ace_v1x-regs.h>

0
soc/xtensa/intel_adsp/common/include/cavs-shim.h → soc/xtensa/intel_adsp/ace_v1x/include/adsp_shim.h
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2
soc/xtensa/intel_adsp/ace_v1x/soc.c
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@ -9,7 +9,7 @@
#include <ace_v1x-regs.h> #include <ace_v1x-regs.h>
#include <cavs-mem.h> #include <cavs-mem.h>
#include <cavs-shim.h> #include <adsp_shim.h>
#include <cpu_init.h> #include <cpu_init.h>
#include <soc.h> #include <soc.h>
#include <xtensa/hal.h> #include <xtensa/hal.h>

151
soc/xtensa/intel_adsp/cavs_v15/include/adsp_shim.h Normal file
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@ -0,0 +1,151 @@
/*
* Copyright (c) 2021 Intel Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_SOC_INTEL_ADSP_CAVS_SHIM_H_
#define ZEPHYR_SOC_INTEL_ADSP_CAVS_SHIM_H_
/* The "shim" block contains most of the general system control
* registers on cAVS platforms. While the base address changes, it
* has remained largely, but not perfectly, compatible between
* versions.
*/
#ifndef _ASMLANGUAGE
struct cavs_shim {
uint32_t skuid;
uint32_t _unused0[7];
uint32_t dspwc_lo;
uint32_t dspwc_hi;
uint32_t dspwctcs;
uint32_t _unused1[1];
uint32_t dspwct0c_lo;
uint32_t dspwct0c_hi;
uint32_t dspwct1c_lo;
uint32_t dspwct1c_hi;
uint32_t _unused2[14];
uint32_t clkctl;
uint32_t clksts;
uint32_t hspgctl; /* cAVS 1.5, see cavs_l2lm for 1.8+ */
uint32_t lspgctl; /* cAVS 1.5, see cavs_l2lm for 1.8+ */
uint32_t hsrmctl; /* cAVS 1.5, see cavs_l2lm for 1.8+ */
uint32_t lsrmctl; /* cAVS 1.5, see cavs_l2lm for 1.8+ */
uint16_t pwrctl;
uint16_t pwrsts;
uint32_t lpsctl;
uint32_t lpsdmas0;
uint32_t lpsdmas1;
uint32_t spsreq;
uint32_t ldoctl;
uint32_t _unused3[2];
union {
/* cAVS 1.5 */
struct {
uint32_t hspgists;
uint32_t lspgists;
uint32_t _unused4[2];
};
/* cAVS 1.8+ */
struct {
uint32_t lpsalhss0;
uint32_t lpsalhss1;
uint32_t lpsalhss2;
uint32_t lpsalhss3;
};
};
uint32_t _unused5[4];
uint32_t l2mecs;
uint32_t l2mpat;
uint32_t _unused6[2];
uint32_t ltrc;
uint32_t _unused8[3];
uint32_t dbgo;
uint32_t svcfg;
uint32_t _unused9[2];
};
/* L2 Local Memory control (cAVS 1.8+) */
struct cavs_l2lm {
uint32_t l2lmcap;
uint32_t l2lmpat;
uint32_t _unused0[2];
uint32_t hspgctl0;
uint32_t hsrmctl0;
uint32_t hspgists0;
uint32_t _unused1;
uint32_t hspgctl1;
uint32_t hsrmctl1;
uint32_t hspgists1;
uint32_t _unused2[9];
uint32_t lspgctl;
uint32_t lsrmctl;
uint32_t lspgists;
};
#define CAVS_L2LM (*((volatile struct cavs_l2lm *)DT_REG_ADDR(DT_NODELABEL(l2lm))))
/* Host memory window control. Not strictly part of the shim block. */
struct cavs_win {
uint32_t dmwba;
uint32_t dmwlo;
};
#define CAVS_WIN ((volatile struct cavs_win *)DT_REG_ADDR(DT_NODELABEL(win)))
#endif /* _ASMLANGUAGE */
#define CAVS_SHIM (*((volatile struct cavs_shim *)DT_REG_ADDR(DT_NODELABEL(shim))))
/* cAVS 1.8+ CLKCTL bits */
#define CAVS_CLKCTL_RHROSCC BIT(31) /* Request HP RING oscillator */
#define CAVS_CLKCTL_RXOSCC BIT(30) /* Request XTAL oscillator */
#define CAVS_CLKCTL_RLROSCC BIT(29) /* Request LP RING oscillator */
#define CAVS_CLKCTL_SLIMFDCGB BIT(25) /* Slimbus force dynamic clock gating*/
#define CAVS_CLKCTL_TCPLCG(x) BIT(16+x) /* Set bit: prevent clock gating on core x */
#define CAVS_CLKCTL_SLIMCSS BIT(6) /* Slimbus clock (0: XTAL, 1: Audio) */
#define CAVS_CLKCTL_WOVCRO BIT(4) /* Request WOVCRO clock */
#define CAVS_CLKCTL_WOVCROSC BIT(3) /* WOVCRO select */
#define CAVS_CLKCTL_OCS BIT(2) /* Oscillator clock (0: LP, 1: HP) */
#define CAVS_CLKCTL_LMCS BIT(1) /* LP mem divisor (0: div/2, 1: div/4) */
#define CAVS_CLKCTL_HMCS BIT(0) /* HP mem divisor (0: div/2, 1: div/4) */
/* cAVS 1.5 had a somewhat different CLKCTL (some fields were the same) */
#define CAVS15_CLKCTL_RAPLLC BIT(31)
#define CAVS15_CLKCTL_RFROSCC BIT(29)
#define CAVS15_CLKCTL_HPGPDMAFDCGB BIT(28)
#define CAVS15_CLKCTL_LPGPDMAFDCGB(x) BIT(26+x)
#define CAVS15_CLKCTL_SLIMFDCGB BIT(25)
#define CAVS15_CLKCTL_DMICFDCGB BIT(24)
#define CAVS15_CLKCTL_I2SFDCGB(x) BIT(20+x)
#define CAVS15_CLKCTL_I2SEFDCGB(x) BIT(18+x)
#define CAVS15_CLKCTL_DPCS(div) ((((div)-1) & 3) << 8) /* DSP PLL divisor (1/2/4) */
#define CAVS15_CLKCTL_TCPAPLLS BIT(7)
#define CAVS15_CLKCTL_LDCS BIT(5)
#define CAVS15_CLKCTL_HDCS BIT(4)
#define CAVS15_CLKCTL_LDOCS BIT(3)
#define CAVS15_CLKCTL_HDOCS BIT(2)
#define CAVS15_CLKCTL_LMPCS BIT(1)
#define CAVS15_CLKCTL_HMPCS BIT(0)
#define CAVS15_CLKCTL_DPCS_MASK(x) (0x3 << (8 + (x) * 2))
#define CAVS_PWRCTL_TCPDSPPG(x) BIT(x)
#define CAVS_PWRSTS_PDSPPGS(x) BIT(x)
#ifdef SOC_SERIES_INTEL_CAVS_V25
# define SHIM_LDOCTL_HPSRAM_LDO_ON (3 << 0 | 3 << 16)
# define SHIM_LDOCTL_HPSRAM_LDO_BYPASS BIT(16)
#else
# define SHIM_LDOCTL_HPSRAM_LDO_ON (3 << 0)
# define SHIM_LDOCTL_HPSRAM_LDO_BYPASS BIT(0)
#endif
#define SHIM_LDOCTL_LPSRAM_LDO_ON (3 << 2)
#define SHIM_LDOCTL_LPSRAM_LDO_BYPASS BIT(2)
#define CAVS_DMWBA_ENABLE BIT(0)
#define CAVS_DMWBA_READONLY BIT(1)
#define CAVS_CLKCTL_OSC_SOURCE_MASK BIT_MASK(2)
#define CAVS_CLKCTL_OSC_REQUEST_MASK (~BIT_MASK(28))
#endif /* ZEPHYR_SOC_INTEL_ADSP_CAVS_SHIM_H_ */

151
soc/xtensa/intel_adsp/cavs_v18/include/adsp_shim.h Normal file
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@ -0,0 +1,151 @@
/*
* Copyright (c) 2021 Intel Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_SOC_INTEL_ADSP_CAVS_SHIM_H_
#define ZEPHYR_SOC_INTEL_ADSP_CAVS_SHIM_H_
/* The "shim" block contains most of the general system control
* registers on cAVS platforms. While the base address changes, it
* has remained largely, but not perfectly, compatible between
* versions.
*/
#ifndef _ASMLANGUAGE
struct cavs_shim {
uint32_t skuid;
uint32_t _unused0[7];
uint32_t dspwc_lo;
uint32_t dspwc_hi;
uint32_t dspwctcs;
uint32_t _unused1[1];
uint32_t dspwct0c_lo;
uint32_t dspwct0c_hi;
uint32_t dspwct1c_lo;
uint32_t dspwct1c_hi;
uint32_t _unused2[14];
uint32_t clkctl;
uint32_t clksts;
uint32_t hspgctl; /* cAVS 1.5, see cavs_l2lm for 1.8+ */
uint32_t lspgctl; /* cAVS 1.5, see cavs_l2lm for 1.8+ */
uint32_t hsrmctl; /* cAVS 1.5, see cavs_l2lm for 1.8+ */
uint32_t lsrmctl; /* cAVS 1.5, see cavs_l2lm for 1.8+ */
uint16_t pwrctl;
uint16_t pwrsts;
uint32_t lpsctl;
uint32_t lpsdmas0;
uint32_t lpsdmas1;
uint32_t spsreq;
uint32_t ldoctl;
uint32_t _unused3[2];
union {
/* cAVS 1.5 */
struct {
uint32_t hspgists;
uint32_t lspgists;
uint32_t _unused4[2];
};
/* cAVS 1.8+ */
struct {
uint32_t lpsalhss0;
uint32_t lpsalhss1;
uint32_t lpsalhss2;
uint32_t lpsalhss3;
};
};
uint32_t _unused5[4];
uint32_t l2mecs;
uint32_t l2mpat;
uint32_t _unused6[2];
uint32_t ltrc;
uint32_t _unused8[3];
uint32_t dbgo;
uint32_t svcfg;
uint32_t _unused9[2];
};
/* L2 Local Memory control (cAVS 1.8+) */
struct cavs_l2lm {
uint32_t l2lmcap;
uint32_t l2lmpat;
uint32_t _unused0[2];
uint32_t hspgctl0;
uint32_t hsrmctl0;
uint32_t hspgists0;
uint32_t _unused1;
uint32_t hspgctl1;
uint32_t hsrmctl1;
uint32_t hspgists1;
uint32_t _unused2[9];
uint32_t lspgctl;
uint32_t lsrmctl;
uint32_t lspgists;
};
#define CAVS_L2LM (*((volatile struct cavs_l2lm *)DT_REG_ADDR(DT_NODELABEL(l2lm))))
/* Host memory window control. Not strictly part of the shim block. */
struct cavs_win {
uint32_t dmwba;
uint32_t dmwlo;
};
#define CAVS_WIN ((volatile struct cavs_win *)DT_REG_ADDR(DT_NODELABEL(win)))
#endif /* _ASMLANGUAGE */
#define CAVS_SHIM (*((volatile struct cavs_shim *)DT_REG_ADDR(DT_NODELABEL(shim))))
/* cAVS 1.8+ CLKCTL bits */
#define CAVS_CLKCTL_RHROSCC BIT(31) /* Request HP RING oscillator */
#define CAVS_CLKCTL_RXOSCC BIT(30) /* Request XTAL oscillator */
#define CAVS_CLKCTL_RLROSCC BIT(29) /* Request LP RING oscillator */
#define CAVS_CLKCTL_SLIMFDCGB BIT(25) /* Slimbus force dynamic clock gating*/
#define CAVS_CLKCTL_TCPLCG(x) BIT(16+x) /* Set bit: prevent clock gating on core x */
#define CAVS_CLKCTL_SLIMCSS BIT(6) /* Slimbus clock (0: XTAL, 1: Audio) */
#define CAVS_CLKCTL_WOVCRO BIT(4) /* Request WOVCRO clock */
#define CAVS_CLKCTL_WOVCROSC BIT(3) /* WOVCRO select */
#define CAVS_CLKCTL_OCS BIT(2) /* Oscillator clock (0: LP, 1: HP) */
#define CAVS_CLKCTL_LMCS BIT(1) /* LP mem divisor (0: div/2, 1: div/4) */
#define CAVS_CLKCTL_HMCS BIT(0) /* HP mem divisor (0: div/2, 1: div/4) */
/* cAVS 1.5 had a somewhat different CLKCTL (some fields were the same) */
#define CAVS15_CLKCTL_RAPLLC BIT(31)
#define CAVS15_CLKCTL_RFROSCC BIT(29)
#define CAVS15_CLKCTL_HPGPDMAFDCGB BIT(28)
#define CAVS15_CLKCTL_LPGPDMAFDCGB(x) BIT(26+x)
#define CAVS15_CLKCTL_SLIMFDCGB BIT(25)
#define CAVS15_CLKCTL_DMICFDCGB BIT(24)
#define CAVS15_CLKCTL_I2SFDCGB(x) BIT(20+x)
#define CAVS15_CLKCTL_I2SEFDCGB(x) BIT(18+x)
#define CAVS15_CLKCTL_DPCS(div) ((((div)-1) & 3) << 8) /* DSP PLL divisor (1/2/4) */
#define CAVS15_CLKCTL_TCPAPLLS BIT(7)
#define CAVS15_CLKCTL_LDCS BIT(5)
#define CAVS15_CLKCTL_HDCS BIT(4)
#define CAVS15_CLKCTL_LDOCS BIT(3)
#define CAVS15_CLKCTL_HDOCS BIT(2)
#define CAVS15_CLKCTL_LMPCS BIT(1)
#define CAVS15_CLKCTL_HMPCS BIT(0)
#define CAVS15_CLKCTL_DPCS_MASK(x) (0x3 << (8 + (x) * 2))
#define CAVS_PWRCTL_TCPDSPPG(x) BIT(x)
#define CAVS_PWRSTS_PDSPPGS(x) BIT(x)
#ifdef SOC_SERIES_INTEL_CAVS_V25
# define SHIM_LDOCTL_HPSRAM_LDO_ON (3 << 0 | 3 << 16)
# define SHIM_LDOCTL_HPSRAM_LDO_BYPASS BIT(16)
#else
# define SHIM_LDOCTL_HPSRAM_LDO_ON (3 << 0)
# define SHIM_LDOCTL_HPSRAM_LDO_BYPASS BIT(0)
#endif
#define SHIM_LDOCTL_LPSRAM_LDO_ON (3 << 2)
#define SHIM_LDOCTL_LPSRAM_LDO_BYPASS BIT(2)
#define CAVS_DMWBA_ENABLE BIT(0)
#define CAVS_DMWBA_READONLY BIT(1)
#define CAVS_CLKCTL_OSC_SOURCE_MASK BIT_MASK(2)
#define CAVS_CLKCTL_OSC_REQUEST_MASK (~BIT_MASK(28))
#endif /* ZEPHYR_SOC_INTEL_ADSP_CAVS_SHIM_H_ */

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soc/xtensa/intel_adsp/cavs_v20/include/adsp_shim.h Normal file
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/*
* Copyright (c) 2021 Intel Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_SOC_INTEL_ADSP_CAVS_SHIM_H_
#define ZEPHYR_SOC_INTEL_ADSP_CAVS_SHIM_H_
/* The "shim" block contains most of the general system control
* registers on cAVS platforms. While the base address changes, it
* has remained largely, but not perfectly, compatible between
* versions.
*/
#ifndef _ASMLANGUAGE
struct cavs_shim {
uint32_t skuid;
uint32_t _unused0[7];
uint32_t dspwc_lo;
uint32_t dspwc_hi;
uint32_t dspwctcs;
uint32_t _unused1[1];
uint32_t dspwct0c_lo;
uint32_t dspwct0c_hi;
uint32_t dspwct1c_lo;
uint32_t dspwct1c_hi;
uint32_t _unused2[14];
uint32_t clkctl;
uint32_t clksts;
uint32_t hspgctl; /* cAVS 1.5, see cavs_l2lm for 1.8+ */
uint32_t lspgctl; /* cAVS 1.5, see cavs_l2lm for 1.8+ */
uint32_t hsrmctl; /* cAVS 1.5, see cavs_l2lm for 1.8+ */
uint32_t lsrmctl; /* cAVS 1.5, see cavs_l2lm for 1.8+ */
uint16_t pwrctl;
uint16_t pwrsts;
uint32_t lpsctl;
uint32_t lpsdmas0;
uint32_t lpsdmas1;
uint32_t spsreq;
uint32_t ldoctl;
uint32_t _unused3[2];
union {
/* cAVS 1.5 */
struct {
uint32_t hspgists;
uint32_t lspgists;
uint32_t _unused4[2];
};
/* cAVS 1.8+ */
struct {
uint32_t lpsalhss0;
uint32_t lpsalhss1;
uint32_t lpsalhss2;
uint32_t lpsalhss3;
};
};
uint32_t _unused5[4];
uint32_t l2mecs;
uint32_t l2mpat;
uint32_t _unused6[2];
uint32_t ltrc;
uint32_t _unused8[3];
uint32_t dbgo;
uint32_t svcfg;
uint32_t _unused9[2];
};
/* L2 Local Memory control (cAVS 1.8+) */
struct cavs_l2lm {
uint32_t l2lmcap;
uint32_t l2lmpat;
uint32_t _unused0[2];
uint32_t hspgctl0;
uint32_t hsrmctl0;
uint32_t hspgists0;
uint32_t _unused1;
uint32_t hspgctl1;
uint32_t hsrmctl1;
uint32_t hspgists1;
uint32_t _unused2[9];
uint32_t lspgctl;
uint32_t lsrmctl;
uint32_t lspgists;
};
#define CAVS_L2LM (*((volatile struct cavs_l2lm *)DT_REG_ADDR(DT_NODELABEL(l2lm))))
/* Host memory window control. Not strictly part of the shim block. */
struct cavs_win {
uint32_t dmwba;
uint32_t dmwlo;
};
#define CAVS_WIN ((volatile struct cavs_win *)DT_REG_ADDR(DT_NODELABEL(win)))
#endif /* _ASMLANGUAGE */
#define CAVS_SHIM (*((volatile struct cavs_shim *)DT_REG_ADDR(DT_NODELABEL(shim))))
/* cAVS 1.8+ CLKCTL bits */
#define CAVS_CLKCTL_RHROSCC BIT(31) /* Request HP RING oscillator */
#define CAVS_CLKCTL_RXOSCC BIT(30) /* Request XTAL oscillator */
#define CAVS_CLKCTL_RLROSCC BIT(29) /* Request LP RING oscillator */
#define CAVS_CLKCTL_SLIMFDCGB BIT(25) /* Slimbus force dynamic clock gating*/
#define CAVS_CLKCTL_TCPLCG(x) BIT(16+x) /* Set bit: prevent clock gating on core x */
#define CAVS_CLKCTL_SLIMCSS BIT(6) /* Slimbus clock (0: XTAL, 1: Audio) */
#define CAVS_CLKCTL_WOVCRO BIT(4) /* Request WOVCRO clock */
#define CAVS_CLKCTL_WOVCROSC BIT(3) /* WOVCRO select */
#define CAVS_CLKCTL_OCS BIT(2) /* Oscillator clock (0: LP, 1: HP) */
#define CAVS_CLKCTL_LMCS BIT(1) /* LP mem divisor (0: div/2, 1: div/4) */
#define CAVS_CLKCTL_HMCS BIT(0) /* HP mem divisor (0: div/2, 1: div/4) */
/* cAVS 1.5 had a somewhat different CLKCTL (some fields were the same) */
#define CAVS15_CLKCTL_RAPLLC BIT(31)
#define CAVS15_CLKCTL_RFROSCC BIT(29)
#define CAVS15_CLKCTL_HPGPDMAFDCGB BIT(28)
#define CAVS15_CLKCTL_LPGPDMAFDCGB(x) BIT(26+x)
#define CAVS15_CLKCTL_SLIMFDCGB BIT(25)
#define CAVS15_CLKCTL_DMICFDCGB BIT(24)
#define CAVS15_CLKCTL_I2SFDCGB(x) BIT(20+x)
#define CAVS15_CLKCTL_I2SEFDCGB(x) BIT(18+x)
#define CAVS15_CLKCTL_DPCS(div) ((((div)-1) & 3) << 8) /* DSP PLL divisor (1/2/4) */
#define CAVS15_CLKCTL_TCPAPLLS BIT(7)
#define CAVS15_CLKCTL_LDCS BIT(5)
#define CAVS15_CLKCTL_HDCS BIT(4)
#define CAVS15_CLKCTL_LDOCS BIT(3)
#define CAVS15_CLKCTL_HDOCS BIT(2)
#define CAVS15_CLKCTL_LMPCS BIT(1)
#define CAVS15_CLKCTL_HMPCS BIT(0)
#define CAVS15_CLKCTL_DPCS_MASK(x) (0x3 << (8 + (x) * 2))
#define CAVS_PWRCTL_TCPDSPPG(x) BIT(x)
#define CAVS_PWRSTS_PDSPPGS(x) BIT(x)
#ifdef SOC_SERIES_INTEL_CAVS_V25
# define SHIM_LDOCTL_HPSRAM_LDO_ON (3 << 0 | 3 << 16)
# define SHIM_LDOCTL_HPSRAM_LDO_BYPASS BIT(16)
#else
# define SHIM_LDOCTL_HPSRAM_LDO_ON (3 << 0)
# define SHIM_LDOCTL_HPSRAM_LDO_BYPASS BIT(0)
#endif
#define SHIM_LDOCTL_LPSRAM_LDO_ON (3 << 2)
#define SHIM_LDOCTL_LPSRAM_LDO_BYPASS BIT(2)
#define CAVS_DMWBA_ENABLE BIT(0)
#define CAVS_DMWBA_READONLY BIT(1)
#define CAVS_CLKCTL_OSC_SOURCE_MASK BIT_MASK(2)
#define CAVS_CLKCTL_OSC_REQUEST_MASK (~BIT_MASK(28))
#endif /* ZEPHYR_SOC_INTEL_ADSP_CAVS_SHIM_H_ */

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soc/xtensa/intel_adsp/cavs_v25/include/adsp_shim.h Normal file
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/*
* Copyright (c) 2021 Intel Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_SOC_INTEL_ADSP_CAVS_SHIM_H_
#define ZEPHYR_SOC_INTEL_ADSP_CAVS_SHIM_H_
/* The "shim" block contains most of the general system control
* registers on cAVS platforms. While the base address changes, it
* has remained largely, but not perfectly, compatible between
* versions.
*/
#ifndef _ASMLANGUAGE
struct cavs_shim {
uint32_t skuid;
uint32_t _unused0[7];
uint32_t dspwc_lo;
uint32_t dspwc_hi;
uint32_t dspwctcs;
uint32_t _unused1[1];
uint32_t dspwct0c_lo;
uint32_t dspwct0c_hi;
uint32_t dspwct1c_lo;
uint32_t dspwct1c_hi;
uint32_t _unused2[14];
uint32_t clkctl;
uint32_t clksts;
uint32_t hspgctl; /* cAVS 1.5, see cavs_l2lm for 1.8+ */
uint32_t lspgctl; /* cAVS 1.5, see cavs_l2lm for 1.8+ */
uint32_t hsrmctl; /* cAVS 1.5, see cavs_l2lm for 1.8+ */
uint32_t lsrmctl; /* cAVS 1.5, see cavs_l2lm for 1.8+ */
uint16_t pwrctl;
uint16_t pwrsts;
uint32_t lpsctl;
uint32_t lpsdmas0;
uint32_t lpsdmas1;
uint32_t spsreq;
uint32_t ldoctl;
uint32_t _unused3[2];
union {
/* cAVS 1.5 */
struct {
uint32_t hspgists;
uint32_t lspgists;
uint32_t _unused4[2];
};
/* cAVS 1.8+ */
struct {
uint32_t lpsalhss0;
uint32_t lpsalhss1;
uint32_t lpsalhss2;
uint32_t lpsalhss3;
};
};
uint32_t _unused5[4];
uint32_t l2mecs;
uint32_t l2mpat;
uint32_t _unused6[2];
uint32_t ltrc;
uint32_t _unused8[3];
uint32_t dbgo;
uint32_t svcfg;
uint32_t _unused9[2];
};
/* L2 Local Memory control (cAVS 1.8+) */
struct cavs_l2lm {
uint32_t l2lmcap;
uint32_t l2lmpat;
uint32_t _unused0[2];
uint32_t hspgctl0;
uint32_t hsrmctl0;
uint32_t hspgists0;
uint32_t _unused1;
uint32_t hspgctl1;
uint32_t hsrmctl1;
uint32_t hspgists1;
uint32_t _unused2[9];
uint32_t lspgctl;
uint32_t lsrmctl;
uint32_t lspgists;
};
#define CAVS_L2LM (*((volatile struct cavs_l2lm *)DT_REG_ADDR(DT_NODELABEL(l2lm))))
/* Host memory window control. Not strictly part of the shim block. */
struct cavs_win {
uint32_t dmwba;
uint32_t dmwlo;
};
#define CAVS_WIN ((volatile struct cavs_win *)DT_REG_ADDR(DT_NODELABEL(win)))
#endif /* _ASMLANGUAGE */
#define CAVS_SHIM (*((volatile struct cavs_shim *)DT_REG_ADDR(DT_NODELABEL(shim))))
/* cAVS 1.8+ CLKCTL bits */
#define CAVS_CLKCTL_RHROSCC BIT(31) /* Request HP RING oscillator */
#define CAVS_CLKCTL_RXOSCC BIT(30) /* Request XTAL oscillator */
#define CAVS_CLKCTL_RLROSCC BIT(29) /* Request LP RING oscillator */
#define CAVS_CLKCTL_SLIMFDCGB BIT(25) /* Slimbus force dynamic clock gating*/
#define CAVS_CLKCTL_TCPLCG(x) BIT(16+x) /* Set bit: prevent clock gating on core x */
#define CAVS_CLKCTL_SLIMCSS BIT(6) /* Slimbus clock (0: XTAL, 1: Audio) */
#define CAVS_CLKCTL_WOVCRO BIT(4) /* Request WOVCRO clock */
#define CAVS_CLKCTL_WOVCROSC BIT(3) /* WOVCRO select */
#define CAVS_CLKCTL_OCS BIT(2) /* Oscillator clock (0: LP, 1: HP) */
#define CAVS_CLKCTL_LMCS BIT(1) /* LP mem divisor (0: div/2, 1: div/4) */
#define CAVS_CLKCTL_HMCS BIT(0) /* HP mem divisor (0: div/2, 1: div/4) */
/* cAVS 1.5 had a somewhat different CLKCTL (some fields were the same) */
#define CAVS15_CLKCTL_RAPLLC BIT(31)
#define CAVS15_CLKCTL_RFROSCC BIT(29)
#define CAVS15_CLKCTL_HPGPDMAFDCGB BIT(28)
#define CAVS15_CLKCTL_LPGPDMAFDCGB(x) BIT(26+x)
#define CAVS15_CLKCTL_SLIMFDCGB BIT(25)
#define CAVS15_CLKCTL_DMICFDCGB BIT(24)
#define CAVS15_CLKCTL_I2SFDCGB(x) BIT(20+x)
#define CAVS15_CLKCTL_I2SEFDCGB(x) BIT(18+x)
#define CAVS15_CLKCTL_DPCS(div) ((((div)-1) & 3) << 8) /* DSP PLL divisor (1/2/4) */
#define CAVS15_CLKCTL_TCPAPLLS BIT(7)
#define CAVS15_CLKCTL_LDCS BIT(5)
#define CAVS15_CLKCTL_HDCS BIT(4)
#define CAVS15_CLKCTL_LDOCS BIT(3)
#define CAVS15_CLKCTL_HDOCS BIT(2)
#define CAVS15_CLKCTL_LMPCS BIT(1)
#define CAVS15_CLKCTL_HMPCS BIT(0)
#define CAVS15_CLKCTL_DPCS_MASK(x) (0x3 << (8 + (x) * 2))
#define CAVS_PWRCTL_TCPDSPPG(x) BIT(x)
#define CAVS_PWRSTS_PDSPPGS(x) BIT(x)
#ifdef SOC_SERIES_INTEL_CAVS_V25
# define SHIM_LDOCTL_HPSRAM_LDO_ON (3 << 0 | 3 << 16)
# define SHIM_LDOCTL_HPSRAM_LDO_BYPASS BIT(16)
#else
# define SHIM_LDOCTL_HPSRAM_LDO_ON (3 << 0)
# define SHIM_LDOCTL_HPSRAM_LDO_BYPASS BIT(0)
#endif
#define SHIM_LDOCTL_LPSRAM_LDO_ON (3 << 2)
#define SHIM_LDOCTL_LPSRAM_LDO_BYPASS BIT(2)
#define CAVS_DMWBA_ENABLE BIT(0)
#define CAVS_DMWBA_READONLY BIT(1)
#define CAVS_CLKCTL_OSC_SOURCE_MASK BIT_MASK(2)
#define CAVS_CLKCTL_OSC_REQUEST_MASK (~BIT_MASK(28))
#endif /* ZEPHYR_SOC_INTEL_ADSP_CAVS_SHIM_H_ */

2
soc/xtensa/intel_adsp/common/boot.c
View file

@ -8,7 +8,7 @@
#include <soc.h> #include <soc.h>
#include <zephyr/arch/xtensa/cache.h> #include <zephyr/arch/xtensa/cache.h>
#include <cavs-shim.h> #include <adsp_shim.h>
#include <cavs-mem.h> #include <cavs-mem.h>
#include <cpu_init.h> #include <cpu_init.h>
#include "manifest.h" #include "manifest.h"

2
soc/xtensa/intel_adsp/common/clk.c
View file

@ -6,7 +6,7 @@
#include <zephyr/device.h> #include <zephyr/device.h>
#include <cavs-clk.h> #include <cavs-clk.h>
#include <cavs-shim.h> #include <adsp_shim.h>
static struct cavs_clock_info platform_clocks[CONFIG_MP_NUM_CPUS]; static struct cavs_clock_info platform_clocks[CONFIG_MP_NUM_CPUS];
static struct k_spinlock lock; static struct k_spinlock lock;

2
soc/xtensa/intel_adsp/common/include/intel_adsp_hda.h
View file

@ -8,7 +8,7 @@
#include <zephyr/arch/xtensa/cache.h> #include <zephyr/arch/xtensa/cache.h>
#include <zephyr/kernel.h> #include <zephyr/kernel.h>
#include <zephyr/device.h> #include <zephyr/device.h>
#include <cavs-shim.h> #include <adsp_shim.h>
#include <cavs-mem.h> #include <cavs-mem.h>
/** /**

2
soc/xtensa/intel_adsp/common/irq.c
View file

@ -9,7 +9,7 @@
#include <zephyr/init.h> #include <zephyr/init.h>
#include <zephyr/logging/log.h> #include <zephyr/logging/log.h>
#include <cavs-shim.h> #include <adsp_shim.h>
#include <cavs-idc.h> #include <cavs-idc.h>
#include "soc.h" #include "soc.h"

2
soc/xtensa/intel_adsp/common/multiprocessing.c
View file

@ -21,7 +21,7 @@ LOG_MODULE_REGISTER(soc_mp, CONFIG_SOC_LOG_LEVEL);
#include <cavs-idc.h> #include <cavs-idc.h>
#include <soc.h> #include <soc.h>
#include <zephyr/arch/xtensa/cache.h> #include <zephyr/arch/xtensa/cache.h>
#include <cavs-shim.h> #include <adsp_shim.h>
#include <cavs-mem.h> #include <cavs-mem.h>
#include <cpu_init.h> #include <cpu_init.h>

2
soc/xtensa/intel_adsp/common/multiprocessing_cavs.c
View file

@ -4,7 +4,7 @@
#include <zephyr/zephyr.h> #include <zephyr/zephyr.h>
#include <cavs-idc.h> #include <cavs-idc.h>
#include <cavs-mem.h> #include <cavs-mem.h>
#include <cavs-shim.h> #include <adsp_shim.h>
/* IDC power up message to the ROM firmware. This isn't documented /* IDC power up message to the ROM firmware. This isn't documented
* anywhere, it's basically just a magic number (except the high bit, * anywhere, it's basically just a magic number (except the high bit,

2
soc/xtensa/intel_adsp/common/soc.c
View file

@ -10,7 +10,7 @@
#include <xtensa/hal.h> #include <xtensa/hal.h>
#include <zephyr/init.h> #include <zephyr/init.h>
#include <cavs-shim.h> #include <adsp_shim.h>
#include <cavs-clk.h> #include <cavs-clk.h>
#include <cavs-idc.h> #include <cavs-idc.h>
#include "soc.h" #include "soc.h"

2
soc/xtensa/intel_adsp/common/sram.c
View file

@ -8,7 +8,7 @@
#include <soc.h> #include <soc.h>
#include <zephyr/arch/xtensa/cache.h> #include <zephyr/arch/xtensa/cache.h>
#include <cavs-shim.h> #include <adsp_shim.h>
#include <cavs-mem.h> #include <cavs-mem.h>
#include <cpu_init.h> #include <cpu_init.h>
#include "manifest.h" #include "manifest.h"