diff --git a/arch/arm/include/aarch32/cortex_m/exc.h b/arch/arm/include/aarch32/cortex_m/exc.h
index 0063bce9a92..05ba19b0c5a 100644
--- a/arch/arm/include/aarch32/cortex_m/exc.h
+++ b/arch/arm/include/aarch32/cortex_m/exc.h
@@ -85,7 +85,7 @@ static ALWAYS_INLINE bool arch_is_in_nested_exception(const z_arch_esf_t *esf)
  */
 static ALWAYS_INLINE void z_arm_exc_setup(void)
 {
-	NVIC_SetPriority(PendSV_IRQn, 0xff);
+	NVIC_SetPriority(PendSV_IRQn, _EXC_PENDSV_PRIO);
 
 #ifdef CONFIG_CPU_CORTEX_M_HAS_BASEPRI
 	/* Note: SVCall IRQ priority level is left to default (0)
diff --git a/include/arch/arm/aarch32/exc.h b/include/arch/arm/aarch32/exc.h
index ba63fc888a1..a633fe0ce77 100644
--- a/include/arch/arm/aarch32/exc.h
+++ b/include/arch/arm/aarch32/exc.h
@@ -14,6 +14,8 @@
 #ifndef ZEPHYR_INCLUDE_ARCH_ARM_AARCH32_EXC_H_
 #define ZEPHYR_INCLUDE_ARCH_ARM_AARCH32_EXC_H_
 
+#include <devicetree.h>
+
 /* for assembler, only works with constants */
 #define Z_EXC_PRIO(pri) (((pri) << (8 - DT_NUM_IRQ_PRIO_BITS)) & 0xff)
 
@@ -32,6 +34,8 @@
  * Regular HW IRQs are always assigned priority levels lower than the priority
  * levels for SVCalls, Zero-Latency IRQs and processor faults.
  *
+ * PendSV IRQ (which is used in Cortex-M variants to implement thread
+ * context-switching) is assigned the lowest IRQ priority level.
  */
 #if defined(CONFIG_CPU_CORTEX_M_HAS_PROGRAMMABLE_FAULT_PRIOS)
 #define _EXCEPTION_RESERVED_PRIO 1
@@ -51,6 +55,10 @@
 
 #define _EXC_IRQ_DEFAULT_PRIO Z_EXC_PRIO(_IRQ_PRIO_OFFSET)
 
+/* Use lowest possible priority level for PendSV */
+#define _EXC_PENDSV_PRIO 0xff
+#define _EXC_PENDSV_PRIO_MASK Z_EXC_PRIO(_EXC_PENDSV_PRIO)
+
 #ifdef _ASMLANGUAGE
 GTEXT(z_arm_exc_exit);
 #else