From 41ecdb9d148088ec12cc7b8ecbca8ce4a6028fec Mon Sep 17 00:00:00 2001 From: Erwan Gouriou Date: Fri, 4 Mar 2022 10:05:59 +0100 Subject: [PATCH] drivers/clock_control: stm32u5: Factorize bus prescalers settings Move prescaler settings to the clock_control_init function. At this step they will be set up twice in PLL case, this will be fixed in a next step. Signed-off-by: Erwan Gouriou --- drivers/clock_control/clock_stm32_ll_u5.c | 24 ++++++----------------- 1 file changed, 6 insertions(+), 18 deletions(-) diff --git a/drivers/clock_control/clock_stm32_ll_u5.c b/drivers/clock_control/clock_stm32_ll_u5.c index e46bc57a4e7..9f610b30fdc 100644 --- a/drivers/clock_control/clock_stm32_ll_u5.c +++ b/drivers/clock_control/clock_stm32_ll_u5.c @@ -244,7 +244,6 @@ static void clock_switch_to_hsi(uint32_t ahb_prescaler) /* Set HSI as SYSCLCK source */ LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_HSI); - LL_RCC_SetAHBPrescaler(ahb_prescaler); while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_HSI) { } } @@ -389,15 +388,9 @@ void config_src_sysclk_hse(LL_UTILS_ClkInitTypeDef s_ClkInitStruct) /* Set HSE as SYSCLCK source */ LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_HSE); - LL_RCC_SetAHBPrescaler(s_ClkInitStruct.AHBCLKDivider); while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_HSE) { } - /* Set peripheral busses prescalers */ - LL_RCC_SetAPB1Prescaler(s_ClkInitStruct.APB1CLKDivider); - LL_RCC_SetAPB2Prescaler(s_ClkInitStruct.APB2CLKDivider); - LL_RCC_SetAPB3Prescaler(s_ClkInitStruct.APB3CLKDivider); - /* If freq not increased, set flash latency after all clock setting */ if (new_hclk_freq <= old_hclk_freq) { LL_SetFlashLatency(new_hclk_freq); @@ -443,15 +436,9 @@ void config_src_sysclk_msis(LL_UTILS_ClkInitTypeDef s_ClkInitStruct) /* Set MSIS as SYSCLCK source */ set_up_clk_msis(); LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_MSIS); - LL_RCC_SetAHBPrescaler(s_ClkInitStruct.AHBCLKDivider); while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_MSIS) { } - /* Set peripheral busses prescalers */ - LL_RCC_SetAPB1Prescaler(s_ClkInitStruct.APB1CLKDivider); - LL_RCC_SetAPB2Prescaler(s_ClkInitStruct.APB2CLKDivider); - LL_RCC_SetAPB3Prescaler(s_ClkInitStruct.APB3CLKDivider); - /* If freq not increased, set flash latency after all clock setting */ if (new_hclk_freq <= old_hclk_freq) { LL_SetFlashLatency(new_hclk_freq); @@ -474,11 +461,6 @@ void config_src_sysclk_hsi(LL_UTILS_ClkInitTypeDef s_ClkInitStruct) clock_switch_to_hsi(s_ClkInitStruct.AHBCLKDivider); - /* Set peripheral busses prescalers */ - LL_RCC_SetAPB1Prescaler(s_ClkInitStruct.APB1CLKDivider); - LL_RCC_SetAPB2Prescaler(s_ClkInitStruct.APB2CLKDivider); - LL_RCC_SetAPB3Prescaler(s_ClkInitStruct.APB3CLKDivider); - /* Set flash latency */ /* HSI used as SYSCLK, set latency to 0 */ LL_FLASH_SetLatency(LL_FLASH_LATENCY_0); @@ -503,6 +485,12 @@ int stm32_clock_control_init(const struct device *dev) /* Some clocks would be activated by default */ config_enable_default_clocks(); + /* Set peripheral busses prescalers */ + LL_RCC_SetAHBPrescaler(ahb_prescaler(STM32_AHB_PRESCALER)); + LL_RCC_SetAPB1Prescaler(apb1_prescaler(STM32_APB1_PRESCALER)); + LL_RCC_SetAPB2Prescaler(apb2_prescaler(STM32_APB2_PRESCALER)); + LL_RCC_SetAPB3Prescaler(apb3_prescaler(STM32_APB3_PRESCALER)); + if (IS_ENABLED(STM32_SYSCLK_SRC_PLL)) { /* Configure PLL as source of SYSCLK */ config_src_sysclk_pll(s_ClkInitStruct);