From 411d8b96247305429e63647b08213cbc9f0de20b Mon Sep 17 00:00:00 2001 From: Andy Ross Date: Thu, 9 Sep 2021 08:20:50 -0700 Subject: [PATCH] soc: intel_adsp: Unify vector table generation This was an abstraction layer without a purpose. All existing platforms have the same (LXn core) layout. When we need to split this out in the future, the right thing will be to use the values already provided by the platform core-isa.h and not duplicate them anyway. Think of this as a first step to an incoming rework of the Zephyr Xtensa interrupt entry generation, which is long overdue. Signed-off-by: Andy Ross --- .../intel_adsp/cavs_v15/include/soc/memory.h | 54 +--------------- soc/xtensa/intel_adsp/cavs_v15/linker.ld | 1 + .../intel_adsp/cavs_v18/include/soc/memory.h | 52 --------------- soc/xtensa/intel_adsp/cavs_v18/linker.ld | 1 + .../intel_adsp/cavs_v20/include/soc/memory.h | 52 --------------- soc/xtensa/intel_adsp/cavs_v20/linker.ld | 1 + .../intel_adsp/cavs_v25/include/soc/memory.h | 52 --------------- soc/xtensa/intel_adsp/cavs_v25/linker.ld | 1 + .../intel_adsp/common/include/cavs-vectors.h | 64 +++++++++++++++++++ 9 files changed, 70 insertions(+), 208 deletions(-) create mode 100644 soc/xtensa/intel_adsp/common/include/cavs-vectors.h diff --git a/soc/xtensa/intel_adsp/cavs_v15/include/soc/memory.h b/soc/xtensa/intel_adsp/cavs_v15/include/soc/memory.h index 4e4b81df4e2..a31077f3d1c 100644 --- a/soc/xtensa/intel_adsp/cavs_v15/include/soc/memory.h +++ b/soc/xtensa/intel_adsp/cavs_v15/include/soc/memory.h @@ -6,6 +6,8 @@ #ifndef __INC_MEMORY_H #define __INC_MEMORY_H +#include + /* L2 HP SRAM */ #define HP_RAM_RESERVE_HEADER_SPACE (HP_SRAM_WIN0_SIZE + \ SRAM_INBOX_SIZE + \ @@ -20,58 +22,6 @@ #define SRAM_BASE (L2_SRAM_BASE) #define SRAM_SIZE (L2_SRAM_SIZE) -/* The reset vector address in SRAM and its size */ -#define XCHAL_RESET_VECTOR0_PADDR_SRAM SRAM_BASE -#define MEM_RESET_TEXT_SIZE 0x268 -#define MEM_RESET_LIT_SIZE 0x8 - -/* This is the base address of all the vectors defined in SRAM */ -#define XCHAL_VECBASE_RESET_PADDR_SRAM \ - (SRAM_BASE + HP_RAM_RESERVE_HEADER_SPACE) - -#define MEM_VECBASE_LIT_SIZE 0x178 - -/* The addresses of the vectors in SRAM. - * Only the memerror vector continues to point to its ROM address. - */ -#define XCHAL_INTLEVEL2_VECTOR_PADDR_SRAM \ - (XCHAL_VECBASE_RESET_PADDR_SRAM + 0x180) - -#define XCHAL_INTLEVEL3_VECTOR_PADDR_SRAM \ - (XCHAL_VECBASE_RESET_PADDR_SRAM + 0x1C0) - -#define XCHAL_INTLEVEL4_VECTOR_PADDR_SRAM \ - (XCHAL_VECBASE_RESET_PADDR_SRAM + 0x200) - -#define XCHAL_INTLEVEL5_VECTOR_PADDR_SRAM \ - (XCHAL_VECBASE_RESET_PADDR_SRAM + 0x240) - -#define XCHAL_INTLEVEL6_VECTOR_PADDR_SRAM \ - (XCHAL_VECBASE_RESET_PADDR_SRAM + 0x280) - -#define XCHAL_INTLEVEL7_VECTOR_PADDR_SRAM \ - (XCHAL_VECBASE_RESET_PADDR_SRAM + 0x2C0) - -#define XCHAL_KERNEL_VECTOR_PADDR_SRAM \ - (XCHAL_VECBASE_RESET_PADDR_SRAM + 0x300) - -#define XCHAL_USER_VECTOR_PADDR_SRAM \ - (XCHAL_VECBASE_RESET_PADDR_SRAM + 0x340) - -#define XCHAL_DOUBLEEXC_VECTOR_PADDR_SRAM \ - (XCHAL_VECBASE_RESET_PADDR_SRAM + 0x3C0) - -#define VECTOR_TBL_SIZE 0x0400 - -/* Vector and literal sizes */ -#define MEM_VECT_LIT_SIZE 0x8 -#define MEM_VECT_TEXT_SIZE 0x38 -#define MEM_VECT_SIZE (MEM_VECT_TEXT_SIZE +\ - MEM_VECT_LIT_SIZE) - -#define MEM_ERROR_TEXT_SIZE 0x180 -#define MEM_ERROR_LIT_SIZE 0x8 - /* text and data share the same L2 HP SRAM. * So, they lie next to each other. */ diff --git a/soc/xtensa/intel_adsp/cavs_v15/linker.ld b/soc/xtensa/intel_adsp/cavs_v15/linker.ld index e486dcacd18..5e3b8b151a3 100644 --- a/soc/xtensa/intel_adsp/cavs_v15/linker.ld +++ b/soc/xtensa/intel_adsp/cavs_v15/linker.ld @@ -18,6 +18,7 @@ OUTPUT_ARCH(xtensa) #include #include #include +#include #include #include diff --git a/soc/xtensa/intel_adsp/cavs_v18/include/soc/memory.h b/soc/xtensa/intel_adsp/cavs_v18/include/soc/memory.h index 3bccafddca2..e810e418567 100644 --- a/soc/xtensa/intel_adsp/cavs_v18/include/soc/memory.h +++ b/soc/xtensa/intel_adsp/cavs_v18/include/soc/memory.h @@ -17,58 +17,6 @@ #define SRAM_BASE (L2_SRAM_BASE) #define SRAM_SIZE (L2_SRAM_SIZE) -/* The reset vector address in SRAM and its size */ -#define XCHAL_RESET_VECTOR0_PADDR_SRAM SRAM_BASE -#define MEM_RESET_TEXT_SIZE 0x268 -#define MEM_RESET_LIT_SIZE 0x8 - -/* This is the base address of all the vectors defined in SRAM */ -#define XCHAL_VECBASE_RESET_PADDR_SRAM \ - (SRAM_BASE + HP_RAM_RESERVE_HEADER_SPACE) - -#define MEM_VECBASE_LIT_SIZE 0x178 - -/* The addresses of the vectors in SRAM. - * Only the memerror vector continues to point to its ROM address. - */ -#define XCHAL_INTLEVEL2_VECTOR_PADDR_SRAM \ - (XCHAL_VECBASE_RESET_PADDR_SRAM + 0x180) - -#define XCHAL_INTLEVEL3_VECTOR_PADDR_SRAM \ - (XCHAL_VECBASE_RESET_PADDR_SRAM + 0x1C0) - -#define XCHAL_INTLEVEL4_VECTOR_PADDR_SRAM \ - (XCHAL_VECBASE_RESET_PADDR_SRAM + 0x200) - -#define XCHAL_INTLEVEL5_VECTOR_PADDR_SRAM \ - (XCHAL_VECBASE_RESET_PADDR_SRAM + 0x240) - -#define XCHAL_INTLEVEL6_VECTOR_PADDR_SRAM \ - (XCHAL_VECBASE_RESET_PADDR_SRAM + 0x280) - -#define XCHAL_INTLEVEL7_VECTOR_PADDR_SRAM \ - (XCHAL_VECBASE_RESET_PADDR_SRAM + 0x2C0) - -#define XCHAL_KERNEL_VECTOR_PADDR_SRAM \ - (XCHAL_VECBASE_RESET_PADDR_SRAM + 0x300) - -#define XCHAL_USER_VECTOR_PADDR_SRAM \ - (XCHAL_VECBASE_RESET_PADDR_SRAM + 0x340) - -#define XCHAL_DOUBLEEXC_VECTOR_PADDR_SRAM \ - (XCHAL_VECBASE_RESET_PADDR_SRAM + 0x3C0) - -#define VECTOR_TBL_SIZE 0x0400 - -/* Vector and literal sizes */ -#define MEM_VECT_LIT_SIZE 0x8 -#define MEM_VECT_TEXT_SIZE 0x38 -#define MEM_VECT_SIZE (MEM_VECT_TEXT_SIZE +\ - MEM_VECT_LIT_SIZE) - -#define MEM_ERROR_TEXT_SIZE 0x180 -#define MEM_ERROR_LIT_SIZE 0x8 - /* text and data share the same L2 HP SRAM. * So, they lie next to each other. */ diff --git a/soc/xtensa/intel_adsp/cavs_v18/linker.ld b/soc/xtensa/intel_adsp/cavs_v18/linker.ld index 3fe01f9108e..da664cf94ef 100644 --- a/soc/xtensa/intel_adsp/cavs_v18/linker.ld +++ b/soc/xtensa/intel_adsp/cavs_v18/linker.ld @@ -18,6 +18,7 @@ OUTPUT_ARCH(xtensa) #include #include #include +#include #include #include diff --git a/soc/xtensa/intel_adsp/cavs_v20/include/soc/memory.h b/soc/xtensa/intel_adsp/cavs_v20/include/soc/memory.h index 6734ae15484..9424eaab62d 100644 --- a/soc/xtensa/intel_adsp/cavs_v20/include/soc/memory.h +++ b/soc/xtensa/intel_adsp/cavs_v20/include/soc/memory.h @@ -17,58 +17,6 @@ #define SRAM_BASE (L2_SRAM_BASE) #define SRAM_SIZE (L2_SRAM_SIZE) -/* The reset vector address in SRAM and its size */ -#define XCHAL_RESET_VECTOR0_PADDR_SRAM SRAM_BASE -#define MEM_RESET_TEXT_SIZE 0x268 -#define MEM_RESET_LIT_SIZE 0x8 - -/* This is the base address of all the vectors defined in SRAM */ -#define XCHAL_VECBASE_RESET_PADDR_SRAM \ - (SRAM_BASE + HP_RAM_RESERVE_HEADER_SPACE) - -#define MEM_VECBASE_LIT_SIZE 0x178 - -/* The addresses of the vectors in SRAM. - * Only the memerror vector continues to point to its ROM address. - */ -#define XCHAL_INTLEVEL2_VECTOR_PADDR_SRAM \ - (XCHAL_VECBASE_RESET_PADDR_SRAM + 0x180) - -#define XCHAL_INTLEVEL3_VECTOR_PADDR_SRAM \ - (XCHAL_VECBASE_RESET_PADDR_SRAM + 0x1C0) - -#define XCHAL_INTLEVEL4_VECTOR_PADDR_SRAM \ - (XCHAL_VECBASE_RESET_PADDR_SRAM + 0x200) - -#define XCHAL_INTLEVEL5_VECTOR_PADDR_SRAM \ - (XCHAL_VECBASE_RESET_PADDR_SRAM + 0x240) - -#define XCHAL_INTLEVEL6_VECTOR_PADDR_SRAM \ - (XCHAL_VECBASE_RESET_PADDR_SRAM + 0x280) - -#define XCHAL_INTLEVEL7_VECTOR_PADDR_SRAM \ - (XCHAL_VECBASE_RESET_PADDR_SRAM + 0x2C0) - -#define XCHAL_KERNEL_VECTOR_PADDR_SRAM \ - (XCHAL_VECBASE_RESET_PADDR_SRAM + 0x300) - -#define XCHAL_USER_VECTOR_PADDR_SRAM \ - (XCHAL_VECBASE_RESET_PADDR_SRAM + 0x340) - -#define XCHAL_DOUBLEEXC_VECTOR_PADDR_SRAM \ - (XCHAL_VECBASE_RESET_PADDR_SRAM + 0x3C0) - -#define VECTOR_TBL_SIZE 0x0400 - -/* Vector and literal sizes */ -#define MEM_VECT_LIT_SIZE 0x8 -#define MEM_VECT_TEXT_SIZE 0x38 -#define MEM_VECT_SIZE (MEM_VECT_TEXT_SIZE +\ - MEM_VECT_LIT_SIZE) - -#define MEM_ERROR_TEXT_SIZE 0x180 -#define MEM_ERROR_LIT_SIZE 0x8 - /* text and data share the same L2 HP SRAM. * So, they lie next to each other. */ diff --git a/soc/xtensa/intel_adsp/cavs_v20/linker.ld b/soc/xtensa/intel_adsp/cavs_v20/linker.ld index 6371b88ae8a..ae4da6520db 100644 --- a/soc/xtensa/intel_adsp/cavs_v20/linker.ld +++ b/soc/xtensa/intel_adsp/cavs_v20/linker.ld @@ -18,6 +18,7 @@ OUTPUT_ARCH(xtensa) #include #include #include +#include #include #include diff --git a/soc/xtensa/intel_adsp/cavs_v25/include/soc/memory.h b/soc/xtensa/intel_adsp/cavs_v25/include/soc/memory.h index 5bdee07c78e..4684137f30b 100644 --- a/soc/xtensa/intel_adsp/cavs_v25/include/soc/memory.h +++ b/soc/xtensa/intel_adsp/cavs_v25/include/soc/memory.h @@ -17,58 +17,6 @@ #define SRAM_BASE (L2_SRAM_BASE) #define SRAM_SIZE (L2_SRAM_SIZE) -/* The reset vector address in SRAM and its size */ -#define XCHAL_RESET_VECTOR0_PADDR_SRAM SRAM_BASE -#define MEM_RESET_TEXT_SIZE 0x268 -#define MEM_RESET_LIT_SIZE 0x8 - -/* This is the base address of all the vectors defined in SRAM */ -#define XCHAL_VECBASE_RESET_PADDR_SRAM \ - (SRAM_BASE + HP_RAM_RESERVE_HEADER_SPACE) - -#define MEM_VECBASE_LIT_SIZE 0x178 - -/* The addresses of the vectors in SRAM. - * Only the memerror vector continues to point to its ROM address. - */ -#define XCHAL_INTLEVEL2_VECTOR_PADDR_SRAM \ - (XCHAL_VECBASE_RESET_PADDR_SRAM + 0x180) - -#define XCHAL_INTLEVEL3_VECTOR_PADDR_SRAM \ - (XCHAL_VECBASE_RESET_PADDR_SRAM + 0x1C0) - -#define XCHAL_INTLEVEL4_VECTOR_PADDR_SRAM \ - (XCHAL_VECBASE_RESET_PADDR_SRAM + 0x200) - -#define XCHAL_INTLEVEL5_VECTOR_PADDR_SRAM \ - (XCHAL_VECBASE_RESET_PADDR_SRAM + 0x240) - -#define XCHAL_INTLEVEL6_VECTOR_PADDR_SRAM \ - (XCHAL_VECBASE_RESET_PADDR_SRAM + 0x280) - -#define XCHAL_INTLEVEL7_VECTOR_PADDR_SRAM \ - (XCHAL_VECBASE_RESET_PADDR_SRAM + 0x2C0) - -#define XCHAL_KERNEL_VECTOR_PADDR_SRAM \ - (XCHAL_VECBASE_RESET_PADDR_SRAM + 0x300) - -#define XCHAL_USER_VECTOR_PADDR_SRAM \ - (XCHAL_VECBASE_RESET_PADDR_SRAM + 0x340) - -#define XCHAL_DOUBLEEXC_VECTOR_PADDR_SRAM \ - (XCHAL_VECBASE_RESET_PADDR_SRAM + 0x3C0) - -#define VECTOR_TBL_SIZE 0x0400 - -/* Vector and literal sizes */ -#define MEM_VECT_LIT_SIZE 0x8 -#define MEM_VECT_TEXT_SIZE 0x38 -#define MEM_VECT_SIZE (MEM_VECT_TEXT_SIZE +\ - MEM_VECT_LIT_SIZE) - -#define MEM_ERROR_TEXT_SIZE 0x180 -#define MEM_ERROR_LIT_SIZE 0x8 - /* text and data share the same L2 HP SRAM. * So, they lie next to each other. */ diff --git a/soc/xtensa/intel_adsp/cavs_v25/linker.ld b/soc/xtensa/intel_adsp/cavs_v25/linker.ld index 1b442ddc10c..620ec0388dd 100644 --- a/soc/xtensa/intel_adsp/cavs_v25/linker.ld +++ b/soc/xtensa/intel_adsp/cavs_v25/linker.ld @@ -18,6 +18,7 @@ OUTPUT_ARCH(xtensa) #include #include #include +#include #include #include diff --git a/soc/xtensa/intel_adsp/common/include/cavs-vectors.h b/soc/xtensa/intel_adsp/common/include/cavs-vectors.h new file mode 100644 index 00000000000..d1b7b7e3341 --- /dev/null +++ b/soc/xtensa/intel_adsp/common/include/cavs-vectors.h @@ -0,0 +1,64 @@ +/* Copyright (c) 2021 Intel Corporation + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef _ZEPHYR_SOC_INTEL_ADSP_VECTORS +#define _ZEPHYR_SOC_INTEL_ADSP_VECTORS + +/* Definitions for our linker script to place and size all the bits of + * the interrupt vector tables. Originally these were SOF-derived and + * part of a platform abstraction layer, but all current hardware has + * the same values. + * + * FIXME: really, we want to be computing this from the core-isa.h + * file, where the offsets from VECBASE are available as + * "XCHAL_*_VECOFS" symbols, etc... There's no reason for us to be + * managing these numbers (nor especially for us to be usurping the + * XCHAL_ namespace to do it!). + */ + +/* This is the base address of all the vectors defined in SRAM */ +#define XCHAL_VECBASE_RESET_PADDR_SRAM \ + (SRAM_BASE + HP_RAM_RESERVE_HEADER_SPACE) + +#define MEM_VECBASE_LIT_SIZE 0x178 + +/* The addresses of the vectors in SRAM. + * Only the memerror vector continues to point to its ROM address. + */ +#define XCHAL_INTLEVEL2_VECTOR_PADDR_SRAM \ + (XCHAL_VECBASE_RESET_PADDR_SRAM + 0x180) + +#define XCHAL_INTLEVEL3_VECTOR_PADDR_SRAM \ + (XCHAL_VECBASE_RESET_PADDR_SRAM + 0x1C0) + +#define XCHAL_INTLEVEL4_VECTOR_PADDR_SRAM \ + (XCHAL_VECBASE_RESET_PADDR_SRAM + 0x200) + +#define XCHAL_INTLEVEL5_VECTOR_PADDR_SRAM \ + (XCHAL_VECBASE_RESET_PADDR_SRAM + 0x240) + +#define XCHAL_INTLEVEL6_VECTOR_PADDR_SRAM \ + (XCHAL_VECBASE_RESET_PADDR_SRAM + 0x280) + +#define XCHAL_INTLEVEL7_VECTOR_PADDR_SRAM \ + (XCHAL_VECBASE_RESET_PADDR_SRAM + 0x2C0) + +#define XCHAL_KERNEL_VECTOR_PADDR_SRAM \ + (XCHAL_VECBASE_RESET_PADDR_SRAM + 0x300) + +#define XCHAL_USER_VECTOR_PADDR_SRAM \ + (XCHAL_VECBASE_RESET_PADDR_SRAM + 0x340) + +#define XCHAL_DOUBLEEXC_VECTOR_PADDR_SRAM \ + (XCHAL_VECBASE_RESET_PADDR_SRAM + 0x3C0) + +#define VECTOR_TBL_SIZE 0x0400 + +/* Vector and literal sizes */ +#define MEM_VECT_LIT_SIZE 0x8 +#define MEM_VECT_TEXT_SIZE 0x38 + +#define MEM_ERROR_TEXT_SIZE 0x180 +#define MEM_ERROR_LIT_SIZE 0x8 + +#endif /* _ZEPHYR_SOC_INTEL_ADSP_VECTORS */