spi: Add QMSI-based implementation
This driver uses the QMSI library and mostly translates calls from the Zephyr API to QMSI ones. This driver conflicts with the native driver implemenation. In order to enable it, you must set: CONFIG_QMSI_DRIVERS=y CONFIG_QMSI_INSTALL_PATH="PATH_TO_QMSI" CONFIG_SPI_QMSI=y CONFIG_SPI_QMSI_PORT_0=y CONFIG_SPI_QMSI_PORT_1=y Missing: - Support for using a GPIO pin as Chip Select; Change-Id: I0d8eca88a2a803b6b3604f396f874313fe90753c Signed-off-by: Vinicius Costa Gomes <vinicius.gomes@intel.com>
This commit is contained in:
Vinicius Costa Gomes
Anas Nashif
parent
416525849a
commit
40f8914376
4 changed files with 351 additions and 0 deletions
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@ -191,6 +191,7 @@ endif
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if SPI
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if SPI
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config SPI_DW
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config SPI_DW
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def_bool y
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def_bool y
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if SPI_DW
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config SPI_DW_CLOCK_GATE
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config SPI_DW_CLOCK_GATE
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def_bool n
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def_bool n
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config SPI_DW_CLOCK_GATE_DRV_NAME
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config SPI_DW_CLOCK_GATE_DRV_NAME
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@ -215,6 +216,21 @@ config SPI_DW_PORT_1_REGS
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default 0xb0001400
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default 0xb0001400
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config SPI_DW_PORT_1_IRQ
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config SPI_DW_PORT_1_IRQ
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default 3
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default 3
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endif # SPI_DW
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config SPI_QMSI
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def_bool n
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if SPI_QMSI
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config SPI_QMSI_PORT_0
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def_bool y
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config SPI_QMSI_PORT_0_IRQ
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default 2
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config SPI_QMSI_PORT_1
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def_bool y
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config SPI_QMSI_PORT_1_IRQ
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default 3
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endif # SPI_QMSI
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endif
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endif
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if WATCHDOG
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if WATCHDOG
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@ -239,6 +239,7 @@ config SPI_DW_CS_GPIO
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config SPI_DW_INIT_PRIORITY
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config SPI_DW_INIT_PRIORITY
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int "Init priority"
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int "Init priority"
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depends on SPI_DW
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default 60
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default 60
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help
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help
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Device driver initialization priority.
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Device driver initialization priority.
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@ -376,4 +377,65 @@ config SPI_DW_PORT_1_PRI
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depends on SPI_DW_PORT_1
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depends on SPI_DW_PORT_1
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default 2
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default 2
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config SPI_QMSI
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bool "QMSI driver for SPI controller"
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depends on SPI && QMSI_DRIVERS
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default n
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help
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SPI driver implementation using QMSI library. QMSI is the
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Quark Microcontroller Software Interface, providing a common
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interface to the Quark family of microcontrollers.
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config SPI_QMSI_PORT_0
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bool
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prompt "QMSI SPI port 0"
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depends on SPI_QMSI
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default n
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help
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Enable QMSI's SPI controller port 0.
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config SPI_QMSI_PORT_0_DRV_NAME
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string
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prompt "QMSI SPI port 0 device name"
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depends on SPI_QMSI_PORT_0
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default "spi_0"
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config SPI_QMSI_PORT_0_IRQ
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int
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prompt "Port 0 interrupt"
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depends on SPI_QMSI_PORT_0
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default 0
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config SPI_QMSI_PORT_0_PRI
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int
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prompt "Port 0 interrupt priority"
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depends on SPI_QMSI_PORT_0
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default 2
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config SPI_QMSI_PORT_1
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bool
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prompt "QMSI SPI port 1"
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depends on SPI_QMSI
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default n
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help
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Enable QMSI's SPI controller port 1.
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config SPI_QMSI_PORT_1_DRV_NAME
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string
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prompt "QMSI SPI port 1 device name"
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depends on SPI_QMSI_PORT_1
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default "spi_1"
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config SPI_QMSI_PORT_1_IRQ
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int
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prompt "Port 1 interrupt"
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depends on SPI_QMSI_PORT_1
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default 0
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config SPI_QMSI_PORT_1_PRI
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int
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prompt "Port 0 interrupt priority"
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depends on SPI_QMSI_PORT_1
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default 2
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endif
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endif
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@ -1,2 +1,4 @@
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ccflags-$(CONFIG_SPI_QMSI) +=-I$(CONFIG_QMSI_INSTALL_PATH)/include
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obj-$(CONFIG_SPI_INTEL) += spi_intel.o
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obj-$(CONFIG_SPI_INTEL) += spi_intel.o
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obj-$(CONFIG_SPI_DW) += spi_dw.o
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obj-$(CONFIG_SPI_DW) += spi_dw.o
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obj-$(CONFIG_SPI_QMSI) += spi_qmsi.o
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271
drivers/spi/spi_qmsi.c
Normal file
271
drivers/spi/spi_qmsi.c
Normal file
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@ -0,0 +1,271 @@
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/*
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* Copyright (c) 2016 Intel Corporation.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#include <device.h>
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#include <drivers/ioapic.h>
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#include <init.h>
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#include <nanokernel.h>
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#include <spi.h>
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#include "qm_scss.h"
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#include "qm_spi.h"
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struct pending_transfer {
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struct device *dev;
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qm_spi_async_transfer_t xfer;
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int counter;
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};
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static struct pending_transfer pending_transfers[QM_SPI_NUM];
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struct spi_qmsi_config {
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qm_spi_t spi;
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};
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struct spi_qmsi_runtime {
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device_sync_call_t sync;
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qm_spi_config_t cfg;
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qm_rc_t rc;
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bool loopback;
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};
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static inline qm_spi_bmode_t config_to_bmode(uint8_t mode)
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{
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switch (mode) {
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case SPI_MODE_CPHA:
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return QM_SPI_BMODE_1;
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case SPI_MODE_CPOL:
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return QM_SPI_BMODE_2;
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case SPI_MODE_CPOL | SPI_MODE_CPHA:
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return QM_SPI_BMODE_3;
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default:
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return QM_SPI_BMODE_0;
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}
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}
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static int spi_qmsi_configure(struct device *dev,
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struct spi_config *config)
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{
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struct spi_qmsi_runtime *context = dev->driver_data;
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qm_spi_config_t *cfg = &context->cfg;
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cfg->frame_size = SPI_WORD_SIZE_GET(config->config) - 1;
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cfg->bus_mode = config_to_bmode(SPI_MODE(config->config));
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/* As loopback is implemented inside the controller,
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* the bus mode doesn't matter.
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*/
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context->loopback = SPI_MODE(config->config) & SPI_MODE_LOOP;
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cfg->clk_divider = config->max_sys_freq;
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/* Will set the configuration before the transfer starts */
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return DEV_OK;
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}
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static void pending_transfer_complete(uint32_t id, qm_rc_t rc)
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{
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struct pending_transfer *pending = &pending_transfers[id];
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struct device *dev = pending->dev;
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struct spi_qmsi_runtime *context;
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qm_spi_config_t *cfg;
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if (!dev)
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return;
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context = dev->driver_data;
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cfg = &context->cfg;
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pending->counter++;
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/*
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* When it is TX/RX transfer this function will be called twice.
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*/
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if (cfg->transfer_mode == QM_SPI_TMOD_TX_RX && pending->counter == 1)
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return;
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pending->dev = NULL;
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pending->counter = 0;
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context->rc = rc;
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device_sync_call_complete(&context->sync);
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}
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static void spi_qmsi_tx_callback(uint32_t id, uint32_t len)
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{
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pending_transfer_complete(id, QM_RC_OK);
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}
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static void spi_qmsi_rx_callback(uint32_t id, uint32_t len)
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{
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pending_transfer_complete(id, QM_RC_OK);
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}
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static void spi_qmsi_err_callback(uint32_t id, qm_rc_t err)
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{
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pending_transfer_complete(id, err);
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}
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static int spi_qmsi_slave_select(struct device *dev, uint32_t slave)
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{
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struct spi_qmsi_config *spi_config = dev->config->config_info;
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qm_spi_t spi = spi_config->spi;
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return qm_spi_slave_select(spi, 1 << (slave - 1)) ? DEV_FAIL : DEV_OK;
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}
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static inline uint8_t frame_size_to_dfs(qm_spi_frame_size_t frame_size)
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{
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if (frame_size <= QM_SPI_FRAME_SIZE_8_BIT)
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return 1;
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if (frame_size <= QM_SPI_FRAME_SIZE_16_BIT)
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return 2;
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if (frame_size <= QM_SPI_FRAME_SIZE_32_BIT)
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return 4;
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/* This should never happen, it will crash later on. */
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return 0;
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}
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static int spi_qmsi_transceive(struct device *dev,
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uint8_t *tx_buf, uint32_t tx_buf_len,
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uint8_t *rx_buf, uint32_t rx_buf_len)
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{
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struct spi_qmsi_config *spi_config = dev->config->config_info;
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qm_spi_t spi = spi_config->spi;
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struct spi_qmsi_runtime *context = dev->driver_data;
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qm_spi_config_t *cfg = &context->cfg;
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uint8_t dfs = frame_size_to_dfs(cfg->frame_size);
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qm_spi_async_transfer_t *xfer;
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qm_rc_t rc;
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if (pending_transfers[spi].dev)
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return DEV_USED;
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pending_transfers[spi].dev = dev;
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xfer = &pending_transfers[spi].xfer;
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xfer->rx = rx_buf;
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xfer->rx_len = rx_buf_len / dfs;
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xfer->tx = tx_buf;
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xfer->tx_len = tx_buf_len / dfs;
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xfer->id = spi;
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xfer->tx_callback = spi_qmsi_tx_callback;
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xfer->rx_callback = spi_qmsi_rx_callback;
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xfer->err_callback = spi_qmsi_err_callback;
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if (tx_buf_len == 0)
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cfg->transfer_mode = QM_SPI_TMOD_RX;
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else if (rx_buf_len == 0)
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cfg->transfer_mode = QM_SPI_TMOD_TX;
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else {
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/* FIXME: QMSI expects rx_buf_len and tx_buf_len to
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* have the same size.
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*/
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cfg->transfer_mode = QM_SPI_TMOD_TX_RX;
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}
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if (context->loopback)
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QM_SPI[spi]->ctrlr0 |= BIT(11);
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rc = qm_spi_set_config(spi, cfg);
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if (rc != QM_RC_OK)
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return DEV_INVALID_CONF;
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rc = qm_spi_irq_transfer(spi, xfer);
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if (rc != QM_RC_OK)
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return DEV_FAIL;
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device_sync_call_wait(&context->sync);
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return context->rc ? DEV_FAIL : DEV_OK;
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}
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static int spi_qmsi_suspend(struct device *dev)
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{
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/* FIXME */
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return 0;
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}
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static int spi_qmsi_resume(struct device *dev)
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{
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/* FIXME */
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return 0;
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}
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static struct spi_driver_api spi_qmsi_api = {
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.configure = spi_qmsi_configure,
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.slave_select = spi_qmsi_slave_select,
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.transceive = spi_qmsi_transceive,
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.suspend = spi_qmsi_suspend,
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.resume = spi_qmsi_resume,
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};
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static int spi_qmsi_init(struct device *dev)
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{
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struct spi_qmsi_config *spi_config = dev->config->config_info;
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struct spi_qmsi_runtime *context = dev->driver_data;
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dev->driver_api = &spi_qmsi_api;
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switch (spi_config->spi) {
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case QM_SPI_MST_0:
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IRQ_CONNECT(CONFIG_SPI_QMSI_PORT_0_IRQ,
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CONFIG_SPI_QMSI_PORT_0_PRI, qm_spi_master_0_isr,
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0, IOAPIC_LEVEL | IOAPIC_HIGH);
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irq_enable(CONFIG_SPI_QMSI_PORT_0_IRQ);
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clk_periph_enable(CLK_PERIPH_CLK | CLK_PERIPH_SPI_M0_REGISTER);
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QM_SCSS_INT->int_spi_mst_0_mask &= ~BIT(0);
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break;
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case QM_SPI_MST_1:
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IRQ_CONNECT(CONFIG_SPI_QMSI_PORT_1_IRQ,
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CONFIG_SPI_QMSI_PORT_1_PRI, qm_spi_master_1_isr,
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0, IOAPIC_LEVEL | IOAPIC_HIGH);
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irq_enable(CONFIG_SPI_QMSI_PORT_1_IRQ);
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clk_periph_enable(CLK_PERIPH_CLK | CLK_PERIPH_SPI_M1_REGISTER);
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QM_SCSS_INT->int_spi_mst_1_mask &= ~BIT(0);
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break;
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default:
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return DEV_FAIL;
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}
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device_sync_call_init(&context->sync);
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return DEV_OK;
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}
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#ifdef CONFIG_SPI_QMSI_PORT_0
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static struct spi_qmsi_config spi_qmsi_mst_0_config = {
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.spi = QM_SPI_MST_0,
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};
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static struct spi_qmsi_runtime spi_qmsi_mst_0_runtime;
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DEVICE_INIT(spi_master_0, CONFIG_SPI_QMSI_PORT_0_DRV_NAME,
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spi_qmsi_init, &spi_qmsi_mst_0_runtime, &spi_qmsi_mst_0_config,
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SECONDARY, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
|
||||||
|
|
||||||
|
#endif /* CONFIG_SPI_QMSI_PORT_0 */
|
||||||
|
#ifdef CONFIG_SPI_QMSI_PORT_1
|
||||||
|
|
||||||
|
static struct spi_qmsi_config spi_qmsi_mst_1_config = {
|
||||||
|
.spi = QM_SPI_MST_1,
|
||||||
|
};
|
||||||
|
|
||||||
|
static struct spi_qmsi_runtime spi_qmsi_mst_1_runtime;
|
||||||
|
|
||||||
|
DEVICE_INIT(spi_master_1, CONFIG_SPI_QMSI_PORT_1_DRV_NAME,
|
||||||
|
spi_qmsi_init, &spi_qmsi_mst_1_runtime, &spi_qmsi_mst_1_config,
|
||||||
|
SECONDARY, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
|
||||||
|
|
||||||
|
#endif /* CONFIG_SPI_QMSI_PORT_1 */
|
||||||
Loading…
Add table
Add a link
Reference in a new issue