board/nsim: Add support of multi-core ARC HS platform in nSIM

Now when SMP support for ARC is available we may introduce a simulation
platform which might be used for testing & development for SMP setups.

One important note is stand-alone nSIM (as well as its "Free" flavour)
doesn't support SMP simulation so we have to switch to use of nSIM via
proprietary MetaWare debugger [1] and so:
 1. We introduce new emulation target "mdb"
 2. It's only possible to run that platform for those who
    have MetaWare tools installed and valid license.

Though QEMU port for ARC is in work at the moment and once we
open that port and it has SMP support we'll switch to it and everybody
will be able to try ARC HS with SMP.

[1] https://www.synopsys.com/dw/ipdir.php?ds=sw_metaware

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>

boards/arc/nsim/board.cmake

@@ -1,9 +1,15 @@
 # SPDX-License-Identifier: Apache-2.0
 
+if(${CONFIG_SOC_NSIM_HS_SMP})
+set(EMU_PLATFORM mdb)
+else()
 set(EMU_PLATFORM nsim)
+endif()
 
+if(NOT ${CONFIG_SOC_NSIM_HS_SMP})
 board_set_flasher_ifnset(arc-nsim)
 board_set_debugger_ifnset(arc-nsim)
+endif()
 
 if(${CONFIG_SOC_NSIM_EM})
 board_runner_args(arc-nsim "--props=nsim_em.props")

boards/arc/nsim/doc/index.rst

@@ -13,16 +13,18 @@ ARC EM or ARC HS based board including the following features:
 * ARC internal timer
 * a virtual output only console (uart-nsim)
 
-There are three supported board sub-configurations:
+There are four supported board sub-configurations:
 
 * ``nsim_em`` which includes normal ARC EM features and ARC MPUv2
 * ``nsim_sem`` which includes secure ARC EM features and ARC MPUv3
 * ``nsim_hs`` which includes base ARC HS features, i.e. w/o PMU and MMU
+* ``nsim_hs_smp`` which includes base ARC HS features in multi-core cluster, still w/o PMU and MMU
 
 For detailed arc features, please refer to
 :zephyr_file:`boards/arc/nsim/support/nsim_em.props`,
-:zephyr_file:`boards/arc/nsim/support/nsim_sem.props` and
-:zephyr_file:`boards/arc/nsim/support/nsim_hs.props`.
+:zephyr_file:`boards/arc/nsim/support/nsim_sem.props`,
+:zephyr_file:`boards/arc/nsim/support/nsim_hs.props` and
+:zephyr_file:`boards/arc/nsim/support/mdb_hs_smp.args`
 
 
 Hardware

boards/arc/nsim/nsim_hs_smp.dts

@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2019, Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include "nsim.dtsi"
+
+/ {
+	model = "snps,nsim_hs";
+	compatible = "snps,nsim_hs";
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "snps,archs";
+			reg = <0>;
+		};
+
+		cpu@1 {
+			device_type = "cpu";
+			compatible = "snps,archs";
+			reg = <1>;
+		};
+	};
+};

boards/arc/nsim/nsim_hs_smp.yaml

@@ -0,0 +1,11 @@
+identifier: nsim_hs_smp
+name: Multi-core HS nSIM simulator
+type: mcu
+simulation: nsim
+arch: arc
+toolchain:
+  - zephyr
+testing:
+  ignore_tags:
+    - net
+    - bluetooth

boards/arc/nsim/nsim_hs_smp_defconfig

@@ -0,0 +1,18 @@
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_ARC=y
+CONFIG_CPU_ARCHS=y
+CONFIG_SOC_NSIM=y
+CONFIG_SOC_NSIM_HS_SMP=y
+CONFIG_BOARD_NSIM=y
+CONFIG_SYS_CLOCK_TICKS_PER_SEC=100
+CONFIG_XIP=n
+CONFIG_BUILD_OUTPUT_BIN=n
+CONFIG_PRINTK=y
+CONFIG_ARCV2_INTERRUPT_UNIT=y
+CONFIG_ARCV2_TIMER=y
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+CONFIG_SERIAL=y
+CONFIG_ARC_EXCEPTION_DEBUG=y
+CONFIG_SMP=y

boards/arc/nsim/support/mdb_hs_smp.args

@@ -0,0 +1,51 @@
+	-arcv2hs
+	-core2
+	-rgf_num_banks=2
+	-rgf_banked_regs=32
+	-rgf_num_wr_ports=2
+	-Xatomic
+	-Xll64
+	-Xunaligned
+	-Xcode_density
+	-Xdiv_rem=radix4
+	-Xswap
+	-Xbitscan
+	-Xmpy_option=qmpyh
+	-Xshift_assist
+	-Xbarrel_shifter
+	-Xfpud_div
+	-Xfpu_mac
+	-Xtimer0
+	-Xtimer0_level=1
+	-Xtimer1
+	-Xtimer1_level=0
+	-Xrtc
+	-action_points=8
+	-Xstack_check
+	-interrupts=72
+	-interrupt_priorities=2
+	-ext_interrupts=70
+	-interrupt_base=0x0
+	-dcache=65536,64,2,a
+	-dcache_feature=2
+	-dcache_uncached_region
+	-dcache_mem_cycles=2
+	-icache=65536,64,4,a
+	-icache_feature=2
+	-arconnect
+	-connect_ics=1
+	-connect_ics_num_semas=16
+	-connect_icm=1
+	-connect_icm_sram_size=512
+	-connect_icm_sram_prot=none
+	-connect_pmu=1
+	-connect_idu=2
+	-connect_idu_cirqnum=64
+	-connect_gfrc=1
+	-connect_icd=2
+	-connect_ici=2
+	-prop=nsim_mem-dev=uart0,base=0xf0000000,irq=0,use_connect=1
+	-on=nsim_print-sys-arch
+	-noprofile
+	-nogoifmain
+	-instrs_per_pass=10