From 405160ca62c5a0731d852ca144ffa52857b39430 Mon Sep 17 00:00:00 2001 From: Manuel Arguelles Date: Fri, 26 May 2023 00:00:00 +0000 Subject: [PATCH] boards: mr_canhubk3: enable LPUART serial driver MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Reuse existing MCUX-based shim driver for LPUART that is compatible with the hardware block in S32K344. DMA is not yet supported. Use the board's debug connector (P6 / LPUART2) as default console. Signed-off-by: Manuel Argüelles --- boards/arm/mr_canhubk3/Kconfig.defconfig | 7 + .../arm/mr_canhubk3/mr_canhubk3-pinctrl.dtsi | 78 ++++++++++- boards/arm/mr_canhubk3/mr_canhubk3.dts | 39 ++++++ boards/arm/mr_canhubk3/mr_canhubk3.yaml | 1 + boards/arm/mr_canhubk3/mr_canhubk3_defconfig | 4 + dts/arm/nxp/nxp_s32k344_m7.dtsi | 129 ++++++++++++++++++ soc/arm/nxp_s32/s32k/Kconfig.series | 2 + 7 files changed, 259 insertions(+), 1 deletion(-) diff --git a/boards/arm/mr_canhubk3/Kconfig.defconfig b/boards/arm/mr_canhubk3/Kconfig.defconfig index 51acd028774..32f28454047 100644 --- a/boards/arm/mr_canhubk3/Kconfig.defconfig +++ b/boards/arm/mr_canhubk3/Kconfig.defconfig @@ -6,4 +6,11 @@ if BOARD_MR_CANHUBK3 config BOARD default "mr_canhubk3" +if SERIAL + +config UART_CONSOLE + default y + +endif # SERIAL + endif # BOARD_MR_CANHUBK3 diff --git a/boards/arm/mr_canhubk3/mr_canhubk3-pinctrl.dtsi b/boards/arm/mr_canhubk3/mr_canhubk3-pinctrl.dtsi index e68d37762b6..2714f448a72 100644 --- a/boards/arm/mr_canhubk3/mr_canhubk3-pinctrl.dtsi +++ b/boards/arm/mr_canhubk3/mr_canhubk3-pinctrl.dtsi @@ -7,11 +7,87 @@ #include &pinctrl { - eirq0_default: eirq0_default { group1 { pinmux = ; input-enable; }; }; + + lpuart0_default: lpuart0_default { + group1 { + pinmux = , ; + output-enable; + }; + group2 { + pinmux = , ; + input-enable; + }; + }; + + lpuart1_default: lpuart1_default { + group1 { + pinmux = , ; + output-enable; + }; + group2 { + pinmux = , ; + input-enable; + }; + }; + + lpuart2_default: lpuart2_default { + group1 { + pinmux = ; + output-enable; + }; + group2 { + pinmux = ; + input-enable; + }; + }; + + lpuart9_default: lpuart9_default { + group1 { + pinmux = ; + output-enable; + }; + group2 { + pinmux = ; + input-enable; + }; + }; + + lpuart10_default: lpuart10_default { + group1 { + pinmux = ; + output-enable; + }; + group2 { + pinmux = ; + input-enable; + }; + }; + + lpuart13_default: lpuart13_default { + group1 { + pinmux = ; + output-enable; + }; + group2 { + pinmux = ; + input-enable; + }; + }; + + lpuart14_default: lpuart14_default { + group1 { + pinmux = ; + output-enable; + }; + group2 { + pinmux = ; + input-enable; + }; + }; }; diff --git a/boards/arm/mr_canhubk3/mr_canhubk3.dts b/boards/arm/mr_canhubk3/mr_canhubk3.dts index e9404acce0c..5a40f2780a8 100644 --- a/boards/arm/mr_canhubk3/mr_canhubk3.dts +++ b/boards/arm/mr_canhubk3/mr_canhubk3.dts @@ -19,6 +19,8 @@ zephyr,itcm = &itcm; zephyr,dtcm = &dtcm; zephyr,code-partition = &code_partition; + zephyr,console = &lpuart2; + zephyr,shell-uart = &lpuart2; }; aliases { @@ -93,3 +95,40 @@ pinctrl-names = "default"; status = "okay"; }; + +&lpuart0 { + pinctrl-0 = <&lpuart0_default>; + pinctrl-names = "default"; +}; + +&lpuart1 { + pinctrl-0 = <&lpuart1_default>; + pinctrl-names = "default"; +}; + +&lpuart2 { + pinctrl-0 = <&lpuart2_default>; + pinctrl-names = "default"; + current-speed = <115200>; + status = "okay"; +}; + +&lpuart9 { + pinctrl-0 = <&lpuart9_default>; + pinctrl-names = "default"; +}; + +&lpuart10 { + pinctrl-0 = <&lpuart10_default>; + pinctrl-names = "default"; +}; + +&lpuart13 { + pinctrl-0 = <&lpuart13_default>; + pinctrl-names = "default"; +}; + +&lpuart14 { + pinctrl-0 = <&lpuart14_default>; + pinctrl-names = "default"; +}; diff --git a/boards/arm/mr_canhubk3/mr_canhubk3.yaml b/boards/arm/mr_canhubk3/mr_canhubk3.yaml index 7d574fbdf65..97abfd20b50 100644 --- a/boards/arm/mr_canhubk3/mr_canhubk3.yaml +++ b/boards/arm/mr_canhubk3/mr_canhubk3.yaml @@ -11,3 +11,4 @@ toolchain: - zephyr supported: - gpio + - uart diff --git a/boards/arm/mr_canhubk3/mr_canhubk3_defconfig b/boards/arm/mr_canhubk3/mr_canhubk3_defconfig index 719bda35605..91ebfcc17d2 100644 --- a/boards/arm/mr_canhubk3/mr_canhubk3_defconfig +++ b/boards/arm/mr_canhubk3/mr_canhubk3_defconfig @@ -20,3 +20,7 @@ CONFIG_NOCACHE_MEMORY=y # Drivers CONFIG_PINCTRL=y +CONFIG_SERIAL=y + +# Serial console +CONFIG_CONSOLE=y diff --git a/dts/arm/nxp/nxp_s32k344_m7.dtsi b/dts/arm/nxp/nxp_s32k344_m7.dtsi index 22496d25e98..6903cb9edb4 100644 --- a/dts/arm/nxp/nxp_s32k344_m7.dtsi +++ b/dts/arm/nxp/nxp_s32k344_m7.dtsi @@ -6,6 +6,7 @@ #include #include +#include / { cpus { @@ -286,6 +287,134 @@ status = "disabled"; }; }; + + lpuart0: uart@40328000 { + compatible = "nxp,kinetis-lpuart"; + reg = <0x40328000 0x4000>; + interrupts = <141 0>; + clocks = <&clock NXP_S32_LPUART0_CLK>; + status = "disabled"; + }; + + lpuart1: uart@4032c000 { + compatible = "nxp,kinetis-lpuart"; + reg = <0x4032c000 0x4000>; + interrupts = <142 0>; + clocks = <&clock NXP_S32_LPUART1_CLK>; + status = "disabled"; + }; + + lpuart2: uart@40330000 { + compatible = "nxp,kinetis-lpuart"; + reg = <0x40330000 0x4000>; + interrupts = <143 0>; + clocks = <&clock NXP_S32_LPUART2_CLK>; + status = "disabled"; + }; + + lpuart3: uart@40334000 { + compatible = "nxp,kinetis-lpuart"; + reg = <0x40334000 0x4000>; + interrupts = <144 0>; + clocks = <&clock NXP_S32_LPUART3_CLK>; + status = "disabled"; + }; + + lpuart4: uart@40338000 { + compatible = "nxp,kinetis-lpuart"; + reg = <0x40338000 0x4000>; + interrupts = <145 0>; + clocks = <&clock NXP_S32_LPUART4_CLK>; + status = "disabled"; + }; + + lpuart5: uart@4033c000 { + compatible = "nxp,kinetis-lpuart"; + reg = <0x4033c000 0x4000>; + interrupts = <146 0>; + clocks = <&clock NXP_S32_LPUART5_CLK>; + status = "disabled"; + }; + + lpuart6: uart@40340000 { + compatible = "nxp,kinetis-lpuart"; + reg = <0x40340000 0x4000>; + interrupts = <147 0>; + clocks = <&clock NXP_S32_LPUART6_CLK>; + status = "disabled"; + }; + + lpuart7: uart@40344000 { + compatible = "nxp,kinetis-lpuart"; + reg = <0x40344000 0x4000>; + interrupts = <148 0>; + clocks = <&clock NXP_S32_LPUART7_CLK>; + status = "disabled"; + }; + + lpuart8: uart@4048c000 { + compatible = "nxp,kinetis-lpuart"; + reg = <0x4048c000 0x4000>; + interrupts = <149 0>; + clocks = <&clock NXP_S32_LPUART8_CLK>; + status = "disabled"; + }; + + lpuart9: uart@40490000 { + compatible = "nxp,kinetis-lpuart"; + reg = <0x40490000 0x4000>; + interrupts = <150 0>; + clocks = <&clock NXP_S32_LPUART9_CLK>; + status = "disabled"; + }; + + lpuart10: uart@40494000 { + compatible = "nxp,kinetis-lpuart"; + reg = <0x40494000 0x4000>; + interrupts = <151 0>; + clocks = <&clock NXP_S32_LPUART10_CLK>; + status = "disabled"; + }; + + lpuart11: uart@40498000 { + compatible = "nxp,kinetis-lpuart"; + reg = <0x40498000 0x4000>; + interrupts = <152 0>; + clocks = <&clock NXP_S32_LPUART11_CLK>; + status = "disabled"; + }; + + lpuart12: uart@4049c000 { + compatible = "nxp,kinetis-lpuart"; + reg = <0x4049c000 0x4000>; + interrupts = <153 0>; + clocks = <&clock NXP_S32_LPUART12_CLK>; + status = "disabled"; + }; + + lpuart13: uart@404a0000 { + compatible = "nxp,kinetis-lpuart"; + reg = <0x404a0000 0x4000>; + interrupts = <154 0>; + clocks = <&clock NXP_S32_LPUART13_CLK>; + status = "disabled"; + }; + + lpuart14: uart@404a4000 { + compatible = "nxp,kinetis-lpuart"; + reg = <0x404a4000 0x4000>; + interrupts = <155 0>; + clocks = <&clock NXP_S32_LPUART14_CLK>; + status = "disabled"; + }; + + lpuart15: uart@404a8000 { + compatible = "nxp,kinetis-lpuart"; + reg = <0x404a8000 0x4000>; + interrupts = <156 0>; + clocks = <&clock NXP_S32_LPUART15_CLK>; + status = "disabled"; + }; }; }; diff --git a/soc/arm/nxp_s32/s32k/Kconfig.series b/soc/arm/nxp_s32/s32k/Kconfig.series index 8629f1b27ea..3bee28013ea 100644 --- a/soc/arm/nxp_s32/s32k/Kconfig.series +++ b/soc/arm/nxp_s32/s32k/Kconfig.series @@ -14,5 +14,7 @@ config SOC_SERIES_S32K3_M7 select PLATFORM_SPECIFIC_INIT if XIP select USE_DT_CODE_PARTITION if XIP select CLOCK_CONTROL + select HAS_MCUX + select HAS_MCUX_LPUART help Enable support for NXP S32K3 MCUs family on Cortex-M7 cores