soc: sensry: Add support for SY120-GBM and SY120-GEN1
Add soc support for Sensry's RISCV32 based SY1xx. Variants of the soc are GBM and GEN1. Signed-off-by: Sven Ginka <s.ginka@sensry.de>
This commit is contained in:
Sven Ginka
Carles Cufí
parent
ec08e1c0e8
commit
402f3d24c4
22 changed files with 1124 additions and 0 deletions
6
soc/sensry/CMakeLists.txt
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6
soc/sensry/CMakeLists.txt
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# SPDX-License-Identifier: Apache-2.0
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# Copyright (c) 2024 sensry.io
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zephyr_include_directories(${SOC_FAMILY}/${SOC_SERIES}/common)
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add_subdirectory_ifdef(CONFIG_SOC_SERIES_SY1XX ganymed/sy1xx)
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8
soc/sensry/Kconfig
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8
soc/sensry/Kconfig
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@ -0,0 +1,8 @@
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# SPDX-License-Identifier: Apache-2.0
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# Copyright (c) 2024 sensry.io
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if SOC_FAMILY_GANYMED
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rsource "*/Kconfig"
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endif # SOC_FAMILY_GANYMED
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8
soc/sensry/Kconfig.defconfig
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8
soc/sensry/Kconfig.defconfig
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# SPDX-License-Identifier: Apache-2.0
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# Copyright (c) 2024 sensry.io
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if SOC_FAMILY_GANYMED
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rsource "*/Kconfig.defconfig"
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endif
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10
soc/sensry/Kconfig.soc
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10
soc/sensry/Kconfig.soc
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@ -0,0 +1,10 @@
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# SPDX-License-Identifier: Apache-2.0
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# Copyright (c) 2024 sensry.io
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config SOC_FAMILY_GANYMED
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bool
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config SOC_FAMILY
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default "ganymed" if SOC_FAMILY_GANYMED
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rsource "*/Kconfig.soc"
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11
soc/sensry/ganymed/Kconfig
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11
soc/sensry/ganymed/Kconfig
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@ -0,0 +1,11 @@
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# SPDX-License-Identifier: Apache-2.0
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# Copyright (c) 2024 sensry.io
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config SOC_FAMILY_GANYMED
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select BUILD_OUTPUT_BIN
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if SOC_SERIES_SY1XX
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rsource "*/Kconfig"
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endif # SOC_SERIES_SY1XX
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8
soc/sensry/ganymed/Kconfig.defconfig
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8
soc/sensry/ganymed/Kconfig.defconfig
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@ -0,0 +1,8 @@
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# SPDX-License-Identifier: Apache-2.0
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# Copyright (c) 2024 sensry.io
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if SOC_SERIES_SY1XX
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rsource "*/Kconfig.defconfig"
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endif
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4
soc/sensry/ganymed/Kconfig.soc
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4
soc/sensry/ganymed/Kconfig.soc
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@ -0,0 +1,4 @@
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# SPDX-License-Identifier: Apache-2.0
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# Copyright (c) 2024 sensry.io
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rsource "*/Kconfig.soc"
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16
soc/sensry/ganymed/sy1xx/CMakeLists.txt
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16
soc/sensry/ganymed/sy1xx/CMakeLists.txt
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@ -0,0 +1,16 @@
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# SPDX-License-Identifier: Apache-2.0
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# Copyright (c) 2024 sensry.io
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zephyr_include_directories(common)
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zephyr_compile_options(-march=rv32imc_zicsr -mabi=ilp32)
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zephyr_sources(
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common/crt0.S
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common/soc.c
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common/udma.c
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)
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zephyr_linker_sources(ROM_START SORT_KEY 0x0vectors common/vector_table.ld)
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set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/common/linker.ld CACHE INTERNAL "")
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10
soc/sensry/ganymed/sy1xx/Kconfig
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10
soc/sensry/ganymed/sy1xx/Kconfig
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# SPDX-License-Identifier: Apache-2.0
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# Copyright (c) 2024 sensry.io
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config SOC_SERIES_SY1XX
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select RISCV
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select RISCV_ISA_RV32I
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select RISCV_ISA_EXT_M
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select RISCV_ISA_EXT_ZICSR
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select RISCV_PRIVILEGED
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select ATOMIC_OPERATIONS_C
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76
soc/sensry/ganymed/sy1xx/Kconfig.defconfig
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76
soc/sensry/ganymed/sy1xx/Kconfig.defconfig
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# SPDX-License-Identifier: Apache-2.0
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# Copyright (c) 2024 sensry.io
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if SOC_SERIES_SY1XX
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config RISCV_PMP
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default n
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config RISCV_HAS_CLIC
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default n
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config RISCV_VECTORED_MODE
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default y
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config INCLUDE_RESET_VECTOR
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default y
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config GEN_IRQ_VECTOR_TABLE
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default y
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config RISCV_GENERIC_TOOLCHAIN
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default y if "$(ZEPHYR_TOOLCHAIN_VARIANT)" = "zephyr"
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config RV_BOOT_HART
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# default cluster id 0x3e, core 0 (FC) => 0x3e0 == 992
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default 992
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config RISCV_SOC_CONTEXT_SAVE
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default n
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config RISCV_SOC_OFFSETS
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default n
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config NUM_IRQS
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default 32
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config RISCV_SOC_INTERRUPT_INIT
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default y
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config RISCV_SOC_HAS_ISR_STACKING
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default n
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config DYNAMIC_INTERRUPTS
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default y
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config GEN_ISR_TABLES
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default y
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config RISCV_MCAUSE_EXCEPTION_MASK
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default 0x1F
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config SYS_CLOCK_HW_CYCLES_PER_SEC
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default 32768
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config SYS_CLOCK_TICKS_PER_SEC
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default 993
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config USE_DT_CODE_PARTITION
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default y
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config RISCV_SOC_HAS_CUSTOM_IRQ_LOCK_OPS
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default n
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config RISCV_SOC_EXCEPTION_FROM_IRQ
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default y
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config INIT_STACKS
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default y
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config XIP
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default n
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config TIMESLICE_SIZE
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default 10
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endif
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21
soc/sensry/ganymed/sy1xx/Kconfig.soc
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21
soc/sensry/ganymed/sy1xx/Kconfig.soc
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# SPDX-License-Identifier: Apache-2.0
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# Copyright (c) 2024 sensry.io
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config SOC_SERIES_SY1XX
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bool
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select SOC_FAMILY_GANYMED
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config SOC_SERIES
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default "sy1xx" if SOC_SERIES_SY1XX
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config SOC_SY120_GBM
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bool
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select SOC_SERIES_SY1XX
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config SOC_SY120_GEN1
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bool
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select SOC_SERIES_SY1XX
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config SOC
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default "sy120_gbm" if SOC_SY120_GBM
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default "sy120_gen1" if SOC_SY120_GEN1
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144
soc/sensry/ganymed/sy1xx/common/crt0.S
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144
soc/sensry/ganymed/sy1xx/common/crt0.S
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@ -0,0 +1,144 @@
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# SPDX-License-Identifier: Apache-2.0
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# Copyright (c) 2024 sensry.io
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#include <zephyr/toolchain.h>
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GTEXT(__initialize)
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# abs 0x0000 - entry point after bootloader
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.section .pre_start, "ax"
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.global __pre_start
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__pre_start:
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jal x0, __prestart_routine
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# abs 0x0080 - will be checked by bootloader
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.section .validity_marker, "ax"
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.word 0xAA551234
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# abs 0x0100 - text
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.section .text, "ax"
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__prestart_routine:
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/* things that will be done prior to actually starting zephyr */
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csrwi mstatus, 0x00
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/* Call into Zephyr initialization. */
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jal x0, __start
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GTEXT(__soc_is_irq)
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SECTION_FUNC(exception.other, __soc_is_irq)
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csrr a0, mcause
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srli a0, a0, 31
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ret
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GTEXT(__soc_handle_irq)
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SECTION_FUNC(exception.other, __soc_handle_irq)
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## clear pending interrupt
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ret
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# we provide a "backup" isr table, if generation (ex. in tests) is disabled
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.global _irq_vector_table
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.weak _irq_vector_table
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.section .text, "ax"
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_irq_vector_table:
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.option norvc;
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j __no_irq_handler0
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j __no_irq_handler1
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j __no_irq_handler2
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j __no_irq_handler3
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j __no_irq_handler4
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j __no_irq_handler5
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j __no_irq_handler6
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j __no_irq_handler7
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j __no_irq_handler8
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j __no_irq_handler9
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j __no_irq_handler10
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j __no_irq_handler11
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j __no_irq_handler12
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j __no_irq_handler13
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j __no_irq_handler14
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j __no_irq_handler15
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j __no_irq_handler16
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j __no_irq_handler17
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j __no_irq_handler18
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j __no_irq_handler19
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j __no_irq_handler20
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j __no_irq_handler21
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j __no_irq_handler22
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j __no_irq_handler23
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j __no_irq_handler24
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j __no_irq_handler25
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j __no_irq_handler26
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j __no_irq_handler27
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j __no_irq_handler28
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j __no_irq_handler29
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j __no_irq_handler30
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j __no_irq_handler31
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__no_irq_handler0:
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j __no_irq_handler0
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__no_irq_handler1:
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j __no_irq_handler1
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__no_irq_handler2:
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j __no_irq_handler2
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__no_irq_handler3:
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j __no_irq_handler3
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__no_irq_handler4:
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j __no_irq_handler4
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__no_irq_handler5:
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j __no_irq_handler5
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__no_irq_handler6:
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j __no_irq_handler6
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__no_irq_handler7:
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j __no_irq_handler7
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__no_irq_handler8:
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j __no_irq_handler8
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__no_irq_handler9:
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j __no_irq_handler9
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__no_irq_handler10:
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j __no_irq_handler10
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__no_irq_handler11:
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j __no_irq_handler11
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__no_irq_handler12:
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j __no_irq_handler12
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__no_irq_handler13:
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j __no_irq_handler13
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__no_irq_handler14:
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j __no_irq_handler14
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__no_irq_handler15:
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j __no_irq_handler15
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__no_irq_handler16:
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j __no_irq_handler16
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__no_irq_handler17:
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j __no_irq_handler17
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__no_irq_handler18:
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j __no_irq_handler18
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__no_irq_handler19:
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j __no_irq_handler19
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__no_irq_handler20:
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j __no_irq_handler20
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__no_irq_handler21:
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j __no_irq_handler21
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__no_irq_handler22:
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j __no_irq_handler22
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__no_irq_handler23:
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j __no_irq_handler23
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__no_irq_handler24:
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j __no_irq_handler24
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__no_irq_handler25:
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j __no_irq_handler25
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__no_irq_handler26:
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j __no_irq_handler26
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__no_irq_handler27:
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j __no_irq_handler27
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__no_irq_handler28:
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j __no_irq_handler28
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__no_irq_handler29:
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j __no_irq_handler29
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__no_irq_handler30:
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j __no_irq_handler30
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__no_irq_handler31:
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j __no_irq_handler31
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255
soc/sensry/ganymed/sy1xx/common/linker.ld
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255
soc/sensry/ganymed/sy1xx/common/linker.ld
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/*
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* Copyright (c) 2013-2014 Wind River Systems, Inc.
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* Copyright (c) 2016-2017 Jean-Paul Etienne <fractalclone@gmail.com>
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* Copyright (c) 2018 Foundries.io Ltd
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* Copyright (c) 2024 sensry.io
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*
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* This file is based on:
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*
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* - include/arch/arm/cortex_m/scripts/linker.ld
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* - include/arch/riscv/common/linker.ld
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* - include/arch/riscv/pulpino/linker.ld
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/devicetree.h>
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#include <zephyr/linker/sections.h>
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#include <zephyr/linker/linker-defs.h>
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#include <zephyr/linker/linker-tool.h>
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#define MPU_ALIGN(region_size) . = ALIGN(4)
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/*
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* Extra efforts would need to be taken to ensure the IRQ handlers are within
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* jumping distance of the vector table in non-XIP builds, so avoid them.
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*/
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#define ROMABLE_REGION ROM
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#define RAMABLE_REGION RAM
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## ROM AREA ##
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#define ROM_BASE 0x1C010100
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#define ROM_SIZE 0x5Fa00
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## RAM AREA ##
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#define RAM_BASE 0x1C070000
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#define RAM_SIZE 0x200000
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MEMORY
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{
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L2_START (rx) : ORIGIN = 0x1c010000, LENGTH = 0x00000080
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L2_VALIDITY (rx) : ORIGIN = 0x1c010080, LENGTH = 0x00000080
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ROM (rx) : ORIGIN = ROM_BASE, LENGTH = ROM_SIZE /* 392kb */
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RAM (rwx) : ORIGIN = RAM_BASE, LENGTH = RAM_SIZE /* 2097kb */
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L2_PRIV_CH0 : ORIGIN = 0x1c004100, LENGTH = 0x2000 /* uDMA access */
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/*
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* Special section, not included in the final binary, used
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* to generate interrupt tables. See include/linker/intlist.ld.
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*/
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IDT_LIST : ORIGIN = 0xFFFFF7FF, LENGTH = 2K
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}
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ENTRY(CONFIG_KERNEL_ENTRY)
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SECTIONS
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{
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.pre_start MAX(0x1c010000,ALIGN(0x80)) :
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{
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KEEP(*(.pre_start))
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} > L2_START
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.validity_marker MAX(0x1c010080,ALIGN(0x80)) :
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{
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KEEP(*(.validity_marker))
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} > L2_VALIDITY
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/* uninitialized space for uDMA access */
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.udma_access (NOLOAD): {
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. = ALIGN(4);
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_udma_space_start = .;
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*(.udma_access)
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_udma_space_end = .;
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} > L2_PRIV_CH0
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#include <zephyr/linker/rel-sections.ld>
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SECTION_PROLOGUE(.plt,,)
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{
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*(.plt)
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}
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SECTION_PROLOGUE(.iplt,,)
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{
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*(.iplt)
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}
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GROUP_START(ROM)
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__rom_region_start = ROM_BASE;
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SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)
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{
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/* Located in generated directory. This file is populated by calling
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* zephyr_linker_sources(ROM_START ...). This typically contains the vector
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* table and debug information.
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*/
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#include <snippets-rom-start.ld>
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__text_region_start = .;
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*(.text .text.*)
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*(.gnu.linkonce.t.*)
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*(.eh_frame)
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} GROUP_LINK_IN(ROM)
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__text_region_end = .;
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__rodata_region_start = .;
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#include <zephyr/linker/common-rom.ld>
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#include <zephyr/linker/thread-local-storage.ld>
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SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)
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{
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. = ALIGN(4);
|
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*(.srodata)
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*(".srodata.*")
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*(.rodata)
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*(.rodata.*)
|
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*(.gnu.linkonce.r.*)
|
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|
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/* Located in generated directory. This file is populated by the
|
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* zephyr_linker_sources() Cmake function.
|
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*/
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#include <snippets-rodata.ld>
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} GROUP_LINK_IN(ROMABLE_REGION)
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|
||||
#include <zephyr/linker/cplusplus-rom.ld>
|
||||
|
||||
__rodata_region_end = .;
|
||||
|
||||
__rom_region_end = .;
|
||||
GROUP_END(ROM)
|
||||
|
||||
GROUP_START(RAM)
|
||||
|
||||
SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_image_ram_start = .;
|
||||
__data_region_start = .;
|
||||
__data_start = .;
|
||||
|
||||
*(.data)
|
||||
*(.data.*)
|
||||
*(.gnu.linkonce.s.*)
|
||||
|
||||
/* https://groups.google.com/a/groups.riscv.org/d/msg/sw-dev/60IdaZj27dY/TKT3hbNlAgAJ */
|
||||
*(.sdata .sdata.* .gnu.linkonce.s.*)
|
||||
*(.sdata2 .sdata2.* .gnu.linkonce.s2.*)
|
||||
|
||||
/* Located in generated directory. This file is populated by the
|
||||
* zephyr_linker_sources() Cmake function.
|
||||
*/
|
||||
#include <snippets-rwdata.ld>
|
||||
|
||||
__data_end = .;
|
||||
|
||||
} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)
|
||||
__data_size = __data_end - __data_start;
|
||||
|
||||
|
||||
__data_load_start = LOADADDR(_DATA_SECTION_NAME);
|
||||
|
||||
#include <zephyr/linker/common-ram.ld>
|
||||
#include <zephyr/linker/cplusplus-ram.ld>
|
||||
|
||||
/* Located in generated directory. This file is populated by the
|
||||
* zephyr_linker_sources() Cmake function.
|
||||
*/
|
||||
#include <snippets-data-sections.ld>
|
||||
|
||||
__data_region_end = .;
|
||||
__data_region_load_start = LOADADDR(_DATA_SECTION_NAME);
|
||||
|
||||
SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)
|
||||
{
|
||||
/*
|
||||
* For performance, BSS section is assumed to be 4 byte aligned and
|
||||
* a multiple of 4 bytes, so it can be cleared in words.
|
||||
*/
|
||||
. = ALIGN(4);
|
||||
__bss_start = .;
|
||||
|
||||
*(.bss .bss.*)
|
||||
*(.sbss .sbss.*)
|
||||
COMMON_SYMBOLS
|
||||
|
||||
/* Ensure 4 byte alignment for the entire section. */
|
||||
. = ALIGN(4);
|
||||
__bss_end = .;
|
||||
} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)
|
||||
|
||||
SECTION_PROLOGUE(_NOINIT_SECTION_NAME,(NOLOAD),)
|
||||
{
|
||||
/*
|
||||
* This section is used for non-initialized objects that
|
||||
* will not be cleared during the boot process.
|
||||
*/
|
||||
*(.noinit .noinit.*)
|
||||
|
||||
/* Located in generated directory. This file is populated by the
|
||||
* zephyr_linker_sources() Cmake function.
|
||||
*/
|
||||
#include <snippets-noinit.ld>
|
||||
|
||||
} GROUP_LINK_IN(RAMABLE_REGION)
|
||||
|
||||
/* Located in generated directory. This file is populated by the
|
||||
* zephyr_linker_sources() Cmake function.
|
||||
*/
|
||||
#include <snippets-ram-sections.ld>
|
||||
|
||||
/* Located in generated directory. This file is populated by the
|
||||
* zephyr_linker_sources() Cmake function.
|
||||
*/
|
||||
#include <snippets-sections.ld>
|
||||
|
||||
#include <zephyr/linker/ram-end.ld>
|
||||
|
||||
GROUP_END(RAMABLE_REGION)
|
||||
|
||||
#ifdef CONFIG_GEN_ISR_TABLES
|
||||
/* Bogus section, post-processed during the build to initialize interrupts. */
|
||||
#include <zephyr/linker/intlist.ld>
|
||||
#endif
|
||||
|
||||
#include <zephyr/linker/debug-sections.ld>
|
||||
|
||||
SECTION_PROLOGUE(.riscv.attributes, 0,)
|
||||
{
|
||||
KEEP(*(.riscv.attributes))
|
||||
KEEP(*(.gnu.attributes))
|
||||
}
|
||||
|
||||
/*
|
||||
* Pulpino toolchains emit these sections; we don't care about them,
|
||||
* but need to avoid build system warnings about orphaned sections.
|
||||
*/
|
||||
SECTION_PROLOGUE(.Pulp_Chip.Info,,)
|
||||
{
|
||||
*(.Pulp_Chip.*)
|
||||
}
|
||||
|
||||
}
|
||||
44
soc/sensry/ganymed/sy1xx/common/pad_ctrl.h
Normal file
44
soc/sensry/ganymed/sy1xx/common/pad_ctrl.h
Normal file
|
|
@ -0,0 +1,44 @@
|
|||
/*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
* Copyright (c) 2024 sensry.io
|
||||
*/
|
||||
|
||||
#ifndef GANYMED_SY1XX_PAD_CTRL_H
|
||||
#define GANYMED_SY1XX_PAD_CTRL_H
|
||||
|
||||
#define PAD_CONFIG(pin_offset, SMT, SLEW, PULLUP, PULLDOWN, DRV, PMOD, DIR) \
|
||||
(((SMT << 7) | (SLEW << 6) | (PULLUP << 5) | (PULLDOWN << 4) | (DRV << 2) | (PMOD << 1) | \
|
||||
DIR) \
|
||||
<< pin_offset)
|
||||
|
||||
#define PAD_CONFIG_ADDR (ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_APB_SOC_CTRL_OFFSET)
|
||||
|
||||
#define PAD_CONFIG_ADDR_UART (PAD_CONFIG_ADDR + 0x020)
|
||||
#define PAD_CONFIG_ADDR_SPI (PAD_CONFIG_ADDR + 0x02c)
|
||||
#define PAD_CONFIG_ADDR_I2C (PAD_CONFIG_ADDR + 0x100)
|
||||
#define PAD_CONFIG_ADDR_MAC (PAD_CONFIG_ADDR + 0x130)
|
||||
|
||||
#define PAD_SMT_DISABLE 0
|
||||
#define PAD_SMT_ENABLE 1
|
||||
|
||||
#define PAD_SLEW_LOW 0
|
||||
#define PAD_SLEW_HIGH 1
|
||||
|
||||
#define PAD_PULLUP_DIS 0
|
||||
#define PAD_PULLUP_EN 1
|
||||
|
||||
#define PAD_PULLDOWN_DIS 0
|
||||
#define PAD_PULLDOWN_EN 1
|
||||
|
||||
#define PAD_DRIVE_2PF 0
|
||||
#define PAD_DRIVE_4PF 1
|
||||
#define PAD_DRIVE_8PF 2
|
||||
#define PAD_DRIVE_16PF 3
|
||||
|
||||
#define PAD_PMOD_NORMAL 0
|
||||
#define PAD_PMOD_TRISTATE 1
|
||||
|
||||
#define PAD_DIR_OUTPUT 0
|
||||
#define PAD_DIR_INPUT 1
|
||||
|
||||
#endif /* GANYMED_SY1XX_PAD_CTRL_H */
|
||||
91
soc/sensry/ganymed/sy1xx/common/soc.c
Normal file
91
soc/sensry/ganymed/sy1xx/common/soc.c
Normal file
|
|
@ -0,0 +1,91 @@
|
|||
/*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
* Copyright (c) 2024 sensry.io
|
||||
*/
|
||||
|
||||
#include <zephyr/device.h>
|
||||
#include <zephyr/init.h>
|
||||
|
||||
#include <zephyr/sys/util.h>
|
||||
|
||||
#define LOG_LEVEL CONFIG_SOC_LOG_LEVEL
|
||||
#include <zephyr/logging/log.h>
|
||||
LOG_MODULE_REGISTER(soc);
|
||||
|
||||
#include "soc.h"
|
||||
|
||||
/* ITC */
|
||||
#define ARCHI_ITC_MASK_OFFSET 0x0
|
||||
#define ARCHI_ITC_MASK_SET_OFFSET 0x4
|
||||
#define ARCHI_ITC_MASK_CLR_OFFSET 0x8
|
||||
#define ARCHI_ITC_STATUS_OFFSET 0xc
|
||||
#define ARCHI_ITC_STATUS_SET_OFFSET 0x10
|
||||
#define ARCHI_ITC_STATUS_CLR_OFFSET 0x14
|
||||
#define ARCHI_ITC_ACK_OFFSET 0x18
|
||||
#define ARCHI_ITC_ACK_SET_OFFSET 0x1c
|
||||
#define ARCHI_ITC_ACK_CLR_OFFSET 0x20
|
||||
#define ARCHI_ITC_FIFO_OFFSET 0x24
|
||||
|
||||
void sys_arch_reboot(int type)
|
||||
{
|
||||
ARG_UNUSED(type);
|
||||
}
|
||||
|
||||
#define ARCHI_REF_CLOCK (32768)
|
||||
#define ARCHI_PER_CLOCK (125000000)
|
||||
|
||||
uint32_t soc_get_rts_clock_frequency(void)
|
||||
{
|
||||
return ARCHI_REF_CLOCK;
|
||||
}
|
||||
|
||||
uint32_t soc_get_peripheral_clock(void)
|
||||
{
|
||||
return ARCHI_PER_CLOCK;
|
||||
}
|
||||
|
||||
void riscv_clic_irq_priority_set(uint32_t irq, uint32_t prio, uint32_t flags)
|
||||
{
|
||||
/* we do not support priorities */
|
||||
}
|
||||
|
||||
void soc_enable_irq(uint32_t idx)
|
||||
{
|
||||
uint32_t current = sys_read32(ARCHI_FC_ITC_ADDR + ARCHI_ITC_MASK_SET_OFFSET);
|
||||
|
||||
sys_write32(current | (1 << (idx & 0x1f)), ARCHI_FC_ITC_ADDR + ARCHI_ITC_MASK_SET_OFFSET);
|
||||
}
|
||||
|
||||
void soc_disable_irq(uint32_t idx)
|
||||
{
|
||||
uint32_t current = sys_read32(ARCHI_FC_ITC_ADDR + ARCHI_ITC_MASK_CLR_OFFSET);
|
||||
|
||||
sys_write32(current & (~(1 << (idx & 0x1f))),
|
||||
ARCHI_FC_ITC_ADDR + ARCHI_ITC_MASK_CLR_OFFSET);
|
||||
}
|
||||
|
||||
/*
|
||||
* SoC-level interrupt initialization. Clear any pending interrupts or
|
||||
* events, and find the INTMUX device if necessary.
|
||||
*
|
||||
* This gets called as almost the first thing z_cstart() does, so it
|
||||
* will happen before any calls to the _arch_irq_xxx() routines above.
|
||||
*/
|
||||
void soc_interrupt_init(void)
|
||||
{
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Perform basic hardware initialization
|
||||
*
|
||||
* Initializes the base clocks and LPFLL using helpers provided by the HAL.
|
||||
*
|
||||
* @return 0
|
||||
*/
|
||||
static int soc_sy1xx_init(void)
|
||||
{
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
SYS_INIT(soc_sy1xx_init, PRE_KERNEL_1, 0);
|
||||
48
soc/sensry/ganymed/sy1xx/common/soc.h
Normal file
48
soc/sensry/ganymed/sy1xx/common/soc.h
Normal file
|
|
@ -0,0 +1,48 @@
|
|||
/*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
* Copyright (c) 2024 sensry.io
|
||||
*/
|
||||
|
||||
#ifndef GANYMED_SY1XX_SOC_H
|
||||
#define GANYMED_SY1XX_SOC_H
|
||||
|
||||
#ifndef _ASMLANGUAGE
|
||||
|
||||
#include <zephyr/types.h>
|
||||
|
||||
/* SOC PERIPHERALS */
|
||||
|
||||
#define ARCHI_SOC_PERIPHERALS_ADDR 0x1A100000
|
||||
|
||||
#define ARCHI_GPIO_OFFSET 0x00001000
|
||||
#define ARCHI_UDMA_OFFSET 0x00002000
|
||||
#define ARCHI_APB_SOC_CTRL_OFFSET 0x00004000
|
||||
#define ARCHI_SOC_EU_OFFSET 0x00006000
|
||||
#define ARCHI_FC_ITC_OFFSET 0x00009800
|
||||
#define ARCHI_FC_TIMER_OFFSET 0x0000B000
|
||||
#define ARCHI_STDOUT_OFFSET 0x0000F000
|
||||
|
||||
#define ARCHI_GPIO_ADDR (ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_GPIO_OFFSET)
|
||||
#define ARCHI_UDMA_ADDR (ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_UDMA_OFFSET)
|
||||
#define ARCHI_APB_SOC_CTRL_ADDR (ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_APB_SOC_CTRL_OFFSET)
|
||||
#define ARCHI_SOC_EU_ADDR (ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_SOC_EU_OFFSET)
|
||||
#define ARCHI_FC_ITC_ADDR (ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_FC_ITC_OFFSET)
|
||||
#define ARCHI_FC_TIMER_ADDR (ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_FC_TIMER_OFFSET)
|
||||
#define ARCHI_STDOUT_ADDR (ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_STDOUT_OFFSET)
|
||||
|
||||
#define ARCHI_PLL_ADDR (ARCHI_SOC_PERIPHERALS_ADDR)
|
||||
#define ARCHI_SECURE_MRAM_CTRL_ADDR 0x1D180000
|
||||
#define ARCHI_GLOBAL_MRAM_CTRL_ADDR 0x1E080000
|
||||
#define ARCHI_MRAM_EFUSE_ADDR 0x1D070100
|
||||
#define ARCHI_TSN_ADDR 0x1A120000
|
||||
#define ARCHI_CAN_ADDR 0x1A130000
|
||||
|
||||
uint32_t soc_get_rts_clock_frequency(void);
|
||||
uint32_t soc_get_peripheral_clock(void);
|
||||
|
||||
void soc_enable_irq(uint32_t idx);
|
||||
void soc_disable_irq(uint32_t idx);
|
||||
|
||||
#endif /* _ASMLANGUAGE */
|
||||
|
||||
#endif /* GANYMED_SY1XX_SOC_H */
|
||||
180
soc/sensry/ganymed/sy1xx/common/udma.c
Normal file
180
soc/sensry/ganymed/sy1xx/common/udma.c
Normal file
|
|
@ -0,0 +1,180 @@
|
|||
/*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
* Copyright (c) 2024 sensry.io
|
||||
*/
|
||||
|
||||
#include "soc.h"
|
||||
#include "udma.h"
|
||||
|
||||
#define UDMA_CTRL_PER_CG (ARCHI_UDMA_ADDR + UDMA_CONF_OFFSET)
|
||||
|
||||
#define DRIVERS_MAX_UART_COUNT 3
|
||||
#define DRIVERS_MAX_I2C_COUNT 4
|
||||
#define DRIVERS_MAX_SPI_COUNT 7
|
||||
#define DEVICE_MAX_ETH_COUNT 1
|
||||
|
||||
void drivers_udma_enable_clock(udma_module_t module, uint32_t instance)
|
||||
{
|
||||
|
||||
uint32_t udma_ctrl_per_cg = sys_read32(UDMA_CTRL_PER_CG);
|
||||
|
||||
switch (module) {
|
||||
|
||||
case DRIVERS_UDMA_UART:
|
||||
if (instance >= DRIVERS_MAX_UART_COUNT) {
|
||||
return;
|
||||
}
|
||||
udma_ctrl_per_cg |= 1 << (instance + 0);
|
||||
break;
|
||||
|
||||
case DRIVERS_UDMA_I2C:
|
||||
if (instance >= DRIVERS_MAX_I2C_COUNT) {
|
||||
return;
|
||||
}
|
||||
udma_ctrl_per_cg |= 1 << (instance + 10);
|
||||
break;
|
||||
|
||||
case DRIVERS_UDMA_SPI:
|
||||
if (instance >= DRIVERS_MAX_SPI_COUNT) {
|
||||
return;
|
||||
}
|
||||
udma_ctrl_per_cg |= 1 << (instance + 3);
|
||||
break;
|
||||
|
||||
case DRIVERS_UDMA_MAC:
|
||||
if (instance >= DEVICE_MAX_ETH_COUNT) {
|
||||
return;
|
||||
}
|
||||
udma_ctrl_per_cg |= 1 << (instance + 20);
|
||||
break;
|
||||
|
||||
case DRIVERS_MAX_UDMA_COUNT:
|
||||
break;
|
||||
}
|
||||
|
||||
sys_write32(udma_ctrl_per_cg, UDMA_CTRL_PER_CG);
|
||||
}
|
||||
|
||||
void drivers_udma_disable_clock(udma_module_t module, uint32_t instance)
|
||||
{
|
||||
|
||||
uint32_t udma_ctrl_per_cg = sys_read32(UDMA_CTRL_PER_CG);
|
||||
|
||||
switch (module) {
|
||||
|
||||
case DRIVERS_UDMA_UART:
|
||||
if (instance >= DRIVERS_MAX_UART_COUNT) {
|
||||
return;
|
||||
}
|
||||
udma_ctrl_per_cg &= ~(1 << (instance + 0));
|
||||
break;
|
||||
|
||||
case DRIVERS_UDMA_I2C:
|
||||
if (instance >= DRIVERS_MAX_I2C_COUNT) {
|
||||
return;
|
||||
}
|
||||
udma_ctrl_per_cg &= ~(1 << (instance + 10));
|
||||
break;
|
||||
|
||||
case DRIVERS_UDMA_SPI:
|
||||
if (instance >= DRIVERS_MAX_SPI_COUNT) {
|
||||
return;
|
||||
}
|
||||
udma_ctrl_per_cg &= ~(1 << (instance + 3));
|
||||
break;
|
||||
|
||||
case DRIVERS_UDMA_MAC:
|
||||
if (instance >= DEVICE_MAX_ETH_COUNT) {
|
||||
return;
|
||||
}
|
||||
udma_ctrl_per_cg &= ~(1 << (instance + 20));
|
||||
break;
|
||||
|
||||
case DRIVERS_MAX_UDMA_COUNT:
|
||||
break;
|
||||
}
|
||||
|
||||
sys_write32(udma_ctrl_per_cg, UDMA_CTRL_PER_CG);
|
||||
}
|
||||
|
||||
void drivers_udma_busy_delay(uint32_t msec)
|
||||
{
|
||||
uint32_t sec = 250000000;
|
||||
uint32_t millis = (sec / 1000) * msec;
|
||||
|
||||
for (uint32_t i = 0; i < millis; i++) {
|
||||
__asm__("nop");
|
||||
}
|
||||
}
|
||||
|
||||
int32_t drivers_udma_cancel(uint32_t base, uint32_t channel)
|
||||
{
|
||||
uint32_t channel_offset = channel == 0 ? 0x00 : 0x10;
|
||||
|
||||
/* clear existing */
|
||||
UDMA_WRITE_REG(base, UDMA_CFG_REG + channel_offset, UDMA_CHANNEL_CFG_CLEAR);
|
||||
return 0;
|
||||
}
|
||||
|
||||
int32_t drivers_udma_is_ready(uint32_t base, uint32_t channel)
|
||||
{
|
||||
uint32_t channel_offset = channel == 0 ? 0x00 : 0x10;
|
||||
|
||||
int32_t isBusy = UDMA_READ_REG(base, UDMA_CFG_REG + channel_offset) & (UDMA_CHANNEL_CFG_EN);
|
||||
|
||||
return isBusy ? 0 : 1;
|
||||
}
|
||||
|
||||
int32_t drivers_udma_wait_for_finished(uint32_t base, uint32_t channel)
|
||||
{
|
||||
uint32_t channel_offset = channel == 0 ? 0x00 : 0x10;
|
||||
|
||||
volatile uint32_t timeout = 200;
|
||||
|
||||
while (UDMA_READ_REG(base, UDMA_CFG_REG + channel_offset) & (UDMA_CHANNEL_CFG_EN)) {
|
||||
drivers_udma_busy_delay(1);
|
||||
timeout--;
|
||||
if (timeout == 0) {
|
||||
return -1;
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int32_t drivers_udma_wait_for_status(uint32_t base)
|
||||
{
|
||||
|
||||
volatile uint32_t timeout = 200;
|
||||
|
||||
while (UDMA_READ_REG(base, UDMA_STATUS) & (0x3)) {
|
||||
drivers_udma_busy_delay(1);
|
||||
timeout--;
|
||||
if (timeout == 0) {
|
||||
return -1;
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int32_t drivers_udma_start(uint32_t base, uint32_t channel, uint32_t saddr, uint32_t size,
|
||||
uint32_t optional_cfg)
|
||||
{
|
||||
uint32_t channel_offset = channel == 0 ? 0x00 : 0x10;
|
||||
|
||||
UDMA_WRITE_REG(base, UDMA_SADDR_REG + channel_offset, saddr);
|
||||
UDMA_WRITE_REG(base, UDMA_SIZE_REG + channel_offset, size);
|
||||
UDMA_WRITE_REG(base, UDMA_CFG_REG + channel_offset, UDMA_CHANNEL_CFG_EN | optional_cfg);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int32_t drivers_udma_get_remaining(uint32_t base, uint32_t channel)
|
||||
{
|
||||
uint32_t channel_offset = channel == 0 ? 0x00 : 0x10;
|
||||
|
||||
int32_t size = UDMA_READ_REG(base, UDMA_SIZE_REG + channel_offset);
|
||||
|
||||
return size;
|
||||
}
|
||||
151
soc/sensry/ganymed/sy1xx/common/udma.h
Normal file
151
soc/sensry/ganymed/sy1xx/common/udma.h
Normal file
|
|
@ -0,0 +1,151 @@
|
|||
/*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
* Copyright (c) 2024 sensry.io
|
||||
*/
|
||||
|
||||
#ifndef GANYMED_SY1XX_UDMA_H
|
||||
#define GANYMED_SY1XX_UDMA_H
|
||||
|
||||
#include <stdint.h>
|
||||
#include <zephyr/arch/common/sys_io.h>
|
||||
#include <soc.h>
|
||||
|
||||
/* UDMA */
|
||||
#define ARCHI_UDMA_ADDR (ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_UDMA_OFFSET)
|
||||
|
||||
#define UDMA_PERIPH_AREA_SIZE_LOG2 7
|
||||
#define UDMA_PERIPH_OFFSET(id) (((id) << UDMA_PERIPH_AREA_SIZE_LOG2))
|
||||
|
||||
#define ARCHI_UDMA_UART_ID(id) (0 + (id))
|
||||
#define ARCHI_UDMA_SPIM_ID(id) (3 + (id))
|
||||
#define ARCHI_UDMA_I2C_ID(id) (10 + (id))
|
||||
#define ARCHI_UDMA_I2S_ID(id) (14 + (id))
|
||||
#define ARCHI_UDMA_HYPER_ID(id) (19 + (id))
|
||||
#define ARCHI_UDMA_TSN_ID(id) (20 + (id))
|
||||
|
||||
#define UDMA_CHANNEL_RX_OFFSET 0x00
|
||||
#define UDMA_CHANNEL_TX_OFFSET 0x10
|
||||
#define UDMA_CHANNEL_CUSTOM_OFFSET 0x20
|
||||
|
||||
/*
|
||||
* For each channel, the RX and TX part have the following registers
|
||||
* The offsets are given relative to the offset of the RX or TX part
|
||||
*/
|
||||
|
||||
/* Start address register */
|
||||
#define UDMA_CHANNEL_SADDR_OFFSET 0x0
|
||||
/* Size register */
|
||||
#define UDMA_CHANNEL_SIZE_OFFSET 0x4
|
||||
/* Configuration register */
|
||||
#define UDMA_CHANNEL_CFG_OFFSET 0x8
|
||||
/* Int configuration register */
|
||||
#define UDMA_CHANNEL_INTCFG_OFFSET 0xC
|
||||
|
||||
/*
|
||||
* The configuration register of the RX and TX parts for each channel can be accessed using the
|
||||
* following bits
|
||||
*/
|
||||
|
||||
#define UDMA_CHANNEL_CFG_SHADOW_BIT (5)
|
||||
#define UDMA_CHANNEL_CFG_CLEAR_BIT (5)
|
||||
#define UDMA_CHANNEL_CFG_EN_BIT (4)
|
||||
#define UDMA_CHANNEL_CFG_SIZE_BIT (1)
|
||||
#define UDMA_CHANNEL_CFG_CONT_BIT (0)
|
||||
|
||||
/* Indicates if a shadow transfer is there */
|
||||
#define UDMA_CHANNEL_CFG_SHADOW (1 << UDMA_CHANNEL_CFG_SHADOW_BIT)
|
||||
/* Stop and clear all pending transfers */
|
||||
#define UDMA_CHANNEL_CFG_CLEAR (1 << UDMA_CHANNEL_CFG_CLEAR_BIT)
|
||||
/* Start a transfer */
|
||||
#define UDMA_CHANNEL_CFG_EN (1 << UDMA_CHANNEL_CFG_EN_BIT)
|
||||
/* Configure for 8-bits transfer */
|
||||
#define UDMA_CHANNEL_CFG_SIZE_8 (0 << UDMA_CHANNEL_CFG_SIZE_BIT)
|
||||
/* Configure for 16-bits transfer */
|
||||
#define UDMA_CHANNEL_CFG_SIZE_16 (1 << UDMA_CHANNEL_CFG_SIZE_BIT)
|
||||
/* Configure for 32-bits transfer */
|
||||
#define UDMA_CHANNEL_CFG_SIZE_32 (2 << UDMA_CHANNEL_CFG_SIZE_BIT)
|
||||
/* Configure for continuous mode */
|
||||
#define UDMA_CHANNEL_CFG_CONT (1 << UDMA_CHANNEL_CFG_CONT_BIT)
|
||||
|
||||
/* Configuration area offset */
|
||||
#define UDMA_CONF_OFFSET 0xF80
|
||||
/* Clock-gating control register */
|
||||
#define UDMA_CONF_CG_OFFSET 0x00
|
||||
|
||||
static inline void plp_udma_cg_set(unsigned int value)
|
||||
{
|
||||
sys_write32(value, ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_UDMA_OFFSET + UDMA_CONF_OFFSET +
|
||||
UDMA_CONF_CG_OFFSET);
|
||||
}
|
||||
|
||||
typedef enum {
|
||||
DRIVERS_UDMA_UART,
|
||||
DRIVERS_UDMA_I2C,
|
||||
DRIVERS_UDMA_SPI,
|
||||
DRIVERS_UDMA_MAC,
|
||||
DRIVERS_MAX_UDMA_COUNT
|
||||
} udma_module_t;
|
||||
|
||||
void drivers_udma_enable_clock(udma_module_t module, uint32_t instance);
|
||||
void drivers_udma_disable_clock(udma_module_t module, uint32_t instance);
|
||||
|
||||
int32_t drivers_udma_cancel(uint32_t base, uint32_t channel);
|
||||
int32_t drivers_udma_is_ready(uint32_t base, uint32_t channel);
|
||||
int32_t drivers_udma_wait_for_finished(uint32_t base, uint32_t channel);
|
||||
int32_t drivers_udma_wait_for_status(uint32_t base);
|
||||
int32_t drivers_udma_start(uint32_t base, uint32_t channel, uint32_t saddr, uint32_t size,
|
||||
uint32_t optional_cfg);
|
||||
int32_t drivers_udma_get_remaining(uint32_t base, uint32_t channel);
|
||||
|
||||
typedef enum {
|
||||
UDMA_SADDR_REG = 0x00,
|
||||
UDMA_SIZE_REG = 0x04,
|
||||
UDMA_CFG_REG = 0x08,
|
||||
|
||||
} udma_regs_t;
|
||||
|
||||
typedef enum {
|
||||
UDMA_RX_SADDR_REG = 0x00,
|
||||
UDMA_RX_SIZE_REG = 0x04,
|
||||
UDMA_RX_CFG_REG = 0x08,
|
||||
|
||||
UDMA_TX_SADDR_REG = 0x10,
|
||||
UDMA_TX_SIZE_REG = 0x14,
|
||||
UDMA_TX_CFG_REG = 0x18,
|
||||
|
||||
UDMA_STATUS = 0x20,
|
||||
UDMA_SETUP_REG = 0x24,
|
||||
} udma_reg_t;
|
||||
|
||||
#define UDMA_RX_DATA_ADDR_INC_SIZE_8 (0x0 << 1)
|
||||
#define UDMA_RX_DATA_ADDR_INC_SIZE_16 (0x1 << 1)
|
||||
#define UDMA_RX_DATA_ADDR_INC_SIZE_32 (0x2 << 1)
|
||||
|
||||
#define UDMA_RX_CHANNEL 0
|
||||
#define UDMA_TX_CHANNEL 1
|
||||
|
||||
#define UDMA_READ_REG(udma_base, reg) sys_read32(udma_base + reg)
|
||||
#define UDMA_WRITE_REG(udma_base, reg, value) sys_write32(value, udma_base + reg)
|
||||
|
||||
#define UDMA_CANCEL_RX(udma_base) drivers_udma_cancel(udma_base, UDMA_RX_CHANNEL)
|
||||
#define UDMA_CANCEL_TX(udma_base) drivers_udma_cancel(udma_base, UDMA_TX_CHANNEL)
|
||||
|
||||
#define UDMA_IS_FINISHED_RX(udma_base) drivers_udma_is_ready(udma_base, UDMA_RX_CHANNEL)
|
||||
#define UDMA_IS_FINISHED_TX(udma_base) drivers_udma_is_ready(udma_base, UDMA_TX_CHANNEL)
|
||||
|
||||
#define UDMA_WAIT_FOR_FINISHED_RX(udma_base) \
|
||||
drivers_udma_wait_for_finished(udma_base, UDMA_RX_CHANNEL)
|
||||
#define UDMA_WAIT_FOR_FINISHED_TX(udma_base) \
|
||||
drivers_udma_wait_for_finished(udma_base, UDMA_TX_CHANNEL)
|
||||
|
||||
#define UDMA_START_RX(base, addr, size, cfg) \
|
||||
drivers_udma_start(base, UDMA_RX_CHANNEL, addr, size, cfg)
|
||||
#define UDMA_START_TX(base, addr, size, cfg) \
|
||||
drivers_udma_start(base, UDMA_TX_CHANNEL, addr, size, cfg)
|
||||
|
||||
#define UDMA_GET_REMAINING_RX(base) drivers_udma_get_remaining(base, UDMA_RX_CHANNEL)
|
||||
#define UDMA_GET_REMAINING_TX(base) drivers_udma_get_remaining(base, UDMA_TX_CHANNEL)
|
||||
|
||||
#define UDMA_WAIT_FOR_STATUS_IDLE(udma_base) drivers_udma_wait_for_status(udma_base)
|
||||
|
||||
#endif /* GANYMED_SY1XX_UDMA_H */
|
||||
14
soc/sensry/ganymed/sy1xx/common/vector_table.ld
Normal file
14
soc/sensry/ganymed/sy1xx/common/vector_table.ld
Normal file
|
|
@ -0,0 +1,14 @@
|
|||
/*
|
||||
* Copyright (c) 2019 Foundries.io Ltd
|
||||
* Copyright (c) 2019 Nordic Semiconductor ASA
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
|
||||
KEEP(*(.reset.*))
|
||||
KEEP(*(".exception.entry.*")) /* contains _isr_wrapper */
|
||||
*(".exception.other.*")
|
||||
|
||||
KEEP(*(.openocd_debug))
|
||||
KEEP(*(".openocd_debug.*"))
|
||||
10
soc/sensry/soc.yml
Normal file
10
soc/sensry/soc.yml
Normal file
|
|
@ -0,0 +1,10 @@
|
|||
# Copyright (c) 2024 sensry.io
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
family:
|
||||
- name: ganymed
|
||||
series:
|
||||
- name: sy1xx
|
||||
socs:
|
||||
- name: sy120_gbm
|
||||
- name: sy120_gen1
|
||||
Loading…
Add table
Add a link
Reference in a new issue