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drivers: remove references to old CAVS platforms

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Remove reference to all dropped CAVS platforms in drivers.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This commit is contained in:
Anas Nashif 2023-04-05 21:38:50 +00:00 • committed by Carles Cufí
commit 402ac9e409
5 changed files with 2 additions and 40 deletions
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24
drivers/dai/intel/dmic/dmic.c
View file

@ -254,53 +254,29 @@ static void dai_dmic_irq_handler(const void *data)
static inline void dai_dmic_dis_clk_gating(const struct dai_intel_dmic *dmic)
{
#ifdef CONFIG_SOC_SERIES_INTEL_CAVS_V15
uint32_t shim_reg;
shim_reg = sys_read32(SHIM_CLKCTL) | SHIM_CLKCTL_DMICFDCGB;
sys_write32(shim_reg, SHIM_CLKCTL);
LOG_INF("dis-dmic-clk-gating CLKCTL %08x", shim_reg);
#else
/* Disable DMIC clock gating */
sys_write32((sys_read32(dmic->shim_base + DMICLCTL_OFFSET) | DMIC_DCGD),
dmic->shim_base + DMICLCTL_OFFSET);
#endif
}
static inline void dai_dmic_en_clk_gating(const struct dai_intel_dmic *dmic)
{
#ifdef CONFIG_SOC_SERIES_INTEL_CAVS_V15
uint32_t shim_reg;
shim_reg = sys_read32(SHIM_CLKCTL) & ~SHIM_CLKCTL_DMICFDCGB;
sys_write32(shim_reg, SHIM_CLKCTL);
LOG_INF("en-dmic-clk-gating CLKCTL %08x", shim_reg);
#else
/* Enable DMIC clock gating */
sys_write32((sys_read32(dmic->shim_base + DMICLCTL_OFFSET) & ~DMIC_DCGD),
dmic->shim_base + DMICLCTL_OFFSET);
#endif
}
static inline void dai_dmic_en_power(const struct dai_intel_dmic *dmic)
{
#ifndef CONFIG_SOC_SERIES_INTEL_CAVS_V15
/* Enable DMIC power */
sys_write32((sys_read32(dmic->shim_base + DMICLCTL_OFFSET) | DMICLCTL_SPA),
dmic->shim_base + DMICLCTL_OFFSET);
#endif
}
static inline void dai_dmic_dis_power(const struct dai_intel_dmic *dmic)
{
#ifndef CONFIG_SOC_SERIES_INTEL_CAVS_V15
/* Disable DMIC power */
sys_write32((sys_read32(dmic->shim_base + DMICLCTL_OFFSET) & (~DMICLCTL_SPA)),
dmic->shim_base + DMICLCTL_OFFSET);
#endif
}
static int dai_dmic_probe(struct dai_intel_dmic *dmic)

7
drivers/dai/intel/dmic/dmic.h
View file

@ -57,13 +57,6 @@
#define TS_LOCAL_OFFS_FRM GET_BITS(15, 12)
#define TS_LOCAL_OFFS_CLK GET_BITS(11, 0)
#ifdef CONFIG_SOC_SERIES_INTEL_CAVS_V15
/* Clock control */
#define SHIM_CLKCTL 0x78
/* DMIC Force Dynamic Clock Gating */
#define SHIM_CLKCTL_DMICFDCGB BIT(24)
#endif
/* Digital Mic Shim Registers */
#define DMICLCTL_OFFSET 0x04
#define DMICIPPTR_OFFSET 0x08

2
drivers/dma/Kconfig.intel_adsp_gpdma
View file

@ -14,7 +14,7 @@ if DMA_INTEL_ADSP_GPDMA
config DMA_INTEL_ADSP_GPDMA_NEED_CONTROLLER_OWNERSHIP
bool
default y if !SOC_INTEL_CAVS_V15
default y
help
Hidden option to indicate that the driver needs to request
dma controller ownership from the host.

8
drivers/interrupt_controller/intc_cavs.c
View file

@ -14,13 +14,7 @@
#include "intc_cavs.h"
#if defined(CONFIG_SMP) && (CONFIG_MP_MAX_NUM_CPUS > 1)
#if defined(CONFIG_SOC_INTEL_CAVS_V15)
#define PER_CPU_OFFSET(x) (0x40 * x)
#elif defined(CONFIG_SOC_INTEL_CAVS_V18)
#define PER_CPU_OFFSET(x) (0x40 * x)
#elif defined(CONFIG_SOC_INTEL_CAVS_V20)
#define PER_CPU_OFFSET(x) (0x40 * x)
#elif defined(CONFIG_SOC_INTEL_CAVS_V25)
#if defined(CONFIG_SOC_INTEL_CAVS_V25)
#define PER_CPU_OFFSET(x) (0x40 * x)
#else
#error "Must define PER_CPU_OFFSET(x) for SoC"

1
drivers/ipm/Kconfig.intel_adsp
View file

@ -51,7 +51,6 @@ config IPM_CAVS_HOST_OUTBOX_OFFSET
config IPM_CAVS_HOST_REGWORD
bool "Store first 4 bytes in IPC register"
depends on INTEL_ADSP_IPC
depends on !SOC_INTEL_CAVS_V15
help
Protocol variant. When true, the first four bytes of a
message are passed in the cAVS IDR/TDR register pair instead