michaelh/zephyr
1
0
Fork 0
Code Releases Activity

drivers/can: move STM32FD clock divider configuration to dts

Browse source 
Remove the CAN_STM32FD_CLOCK_DIVISOR configuration option,
and add configuration via dts property clk-divider instead.

Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
This commit is contained in:
Thomas Stranger 2022-08-12 20:24:42 +02:00 • committed by Fabio Baltieri
commit 402752c07c
3 changed files with 39 additions and 23 deletions
Download patch file Download diff file Expand all files Collapse all files

10
drivers/can/Kconfig.stm32fd
View file

@ -28,14 +28,4 @@ config CAN_MAX_EXT_ID_FILTER
Defines the maximum number of filters with extended ID (29-bit)
that can be attached.
config CAN_STM32FD_CLOCK_DIVISOR
int "CAN clock divisor"
range 1 30
default 1
help
The APB clock is divided by this value (stored in CKDIV register)
before it is fed to the CAN core.
Note that the the divisor affects all CAN controllers.
Allowed values: 1 or 2 * n, where n <= 15.
endif # CAN_STM32FD

22
drivers/can/can_stm32fd.c
View file

@ -18,16 +18,6 @@
LOG_MODULE_REGISTER(can_stm32fd, CONFIG_CAN_LOG_LEVEL);
#ifdef CONFIG_CAN_STM32FD_CLOCK_DIVISOR
#if CONFIG_CAN_STM32FD_CLOCK_DIVISOR != 1 && CONFIG_CAN_STM32FD_CLOCK_DIVISOR & 0x01
#error CAN_STM32FD_CLOCK_DIVISOR invalid. Allowed values are 1 or 2 * n, where n <= 15.
#else
#define CAN_STM32FD_CLOCK_DIVISOR CONFIG_CAN_STM32FD_CLOCK_DIVISOR
#endif /* CONFIG_CAN_STM32FD_CLOCK_DIVISOR */
#else
#define CAN_STM32FD_CLOCK_DIVISOR 1U
#endif /* CONFIG_CAN_STM32FD_CLOCK_DIVISOR*/
#define DT_DRV_COMPAT st_stm32_fdcan
/* This symbol takes the value 1 if one of the device instances */
@ -43,6 +33,7 @@ struct can_stm32fd_config {
const struct stm32_pclken *pclken;
void (*config_irq)(void);
const struct pinctrl_dev_config *pcfg;
uint8_t clock_divider;
};
static int can_stm32fd_get_core_clock(const struct device *dev, uint32_t *rate)
@ -56,7 +47,11 @@ static int can_stm32fd_get_core_clock(const struct device *dev, uint32_t *rate)
return -EIO;
}
*rate = rate_tmp / CAN_STM32FD_CLOCK_DIVISOR;
if (FDCAN_CONFIG->CKDIV == 0) {
*rate = rate_tmp;
} else {
*rate = rate_tmp / (FDCAN_CONFIG->CKDIV << 1);
}
return 0;
}
@ -87,8 +82,10 @@ static int can_stm32fd_clock_enable(const struct device *dev)
return ret;
}
if (stm32fd_cfg->clock_divider != 0) {
can_mcan_enable_configuration_change(dev);
FDCAN_CONFIG->CKDIV = CAN_STM32FD_CLOCK_DIVISOR >> 1;
FDCAN_CONFIG->CKDIV = stm32fd_cfg->clock_divider >> 1;
}
return 0;
}
@ -194,6 +191,7 @@ static void config_can_##inst##_irq(void) \
.pclk_len = DT_INST_NUM_CLOCKS(inst), \
.config_irq = config_can_##inst##_irq, \
.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(inst), \
.clock_divider = DT_INST_PROP_OR(inst, clk_divider, 0) \
}; \
\
static const struct can_mcan_config can_mcan_cfg_##inst = \

28
dts/bindings/can/st,stm32-fdcan.yaml
View file

@ -13,3 +13,31 @@ properties:
clocks:
required: true
clk-divider:
type: int
required: false
enum:
- 1
- 2
- 4
- 6
- 8
- 10
- 12
- 14
- 16
- 18
- 20
- 22
- 24
- 26
- 28
- 30
description: |
Divides the kernel clock giving the time quanta clock that is fed to the
CAN core(FDCAN_CKDIV).
Note that the divisor is common to all 'st,stm32-fdcan' instances.
Divide by 1 is the peripherals reset value and remains set unless
this property is configured.