diff --git a/arch/arm/soc/st_stm32/stm32f4/Kconfig.defconfig.stm32f407xx b/arch/arm/soc/st_stm32/stm32f4/Kconfig.defconfig.stm32f407xx
new file mode 100644
index 00000000000..f359ea5e037
--- /dev/null
+++ b/arch/arm/soc/st_stm32/stm32f4/Kconfig.defconfig.stm32f407xx
@@ -0,0 +1,24 @@
+# Kconfig - ST STM32F407XX MCU configuration options
+#
+# Copyright (c) 2016 Linaro Limited.
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+if SOC_STM32F407XX
+
+config SOC
+	string
+	default stm32f407xx
+
+config SRAM_SIZE
+	default 192
+
+config FLASH_SIZE
+	default 1024
+
+config NUM_IRQS
+	int
+	default 85
+
+endif # SOC_STM32F407XX
diff --git a/arch/arm/soc/st_stm32/stm32f4/Kconfig.defconfig.stm32f429xx b/arch/arm/soc/st_stm32/stm32f4/Kconfig.defconfig.stm32f429xx
new file mode 100644
index 00000000000..a993cdc166a
--- /dev/null
+++ b/arch/arm/soc/st_stm32/stm32f4/Kconfig.defconfig.stm32f429xx
@@ -0,0 +1,24 @@
+# Kconfig - ST STM32F429XX MCU configuration options
+#
+# Copyright (c) 2016 Linaro Limited.
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+if SOC_STM32F429XX
+
+config SOC
+	string
+	default stm32f429xx
+
+config SRAM_SIZE
+	default 256
+
+config FLASH_SIZE
+	default 2048
+
+config NUM_IRQS
+	int
+	default 85
+
+endif # SOC_STM32F429XX
diff --git a/arch/arm/soc/st_stm32/stm32f4/Kconfig.soc b/arch/arm/soc/st_stm32/stm32f4/Kconfig.soc
index a8e5d56fee4..d2b5bd29a09 100644
--- a/arch/arm/soc/st_stm32/stm32f4/Kconfig.soc
+++ b/arch/arm/soc/st_stm32/stm32f4/Kconfig.soc
@@ -15,4 +15,10 @@ config SOC_STM32F401XE
 config SOC_STM32F411XE
 	bool "STM32F411XE"
 
+config SOC_STM32F407XX
+	bool "STM32F407XX"
+
+config SOC_STM32F429XX
+	bool "STM32F429XX"
+
 endchoice
diff --git a/arch/arm/soc/st_stm32/stm32f4/flash_registers.h b/arch/arm/soc/st_stm32/stm32f4/flash_registers.h
index 1f598b8faa7..a0dea61c83c 100644
--- a/arch/arm/soc/st_stm32/stm32f4/flash_registers.h
+++ b/arch/arm/soc/st_stm32/stm32f4/flash_registers.h
@@ -77,6 +77,18 @@ static inline void __setup_flash(void)
 	} else if (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC <= 100000000) {
 		regs->acr.bit.latency = STM32F4X_FLASH_LATENCY_3;
 	}
+#elif defined(CONFIG_SOC_STM32F407XX) || defined(CONFIG_SOC_STM32F429XX)
+	else if (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC <= 60000000) {
+		regs->acr.bit.latency = STM32F4X_FLASH_LATENCY_1;
+	} else if (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC <= 90000000) {
+		regs->acr.bit.latency = STM32F4X_FLASH_LATENCY_2;
+	} else if (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC <= 120000000) {
+		regs->acr.bit.latency = STM32F4X_FLASH_LATENCY_3;
+	} else if (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC <= 150000000) {
+		regs->acr.bit.latency = STM32F4X_FLASH_LATENCY_4;
+	} else if (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC <= 180000000) {
+		regs->acr.bit.latency = STM32F4X_FLASH_LATENCY_5;
+	}
 #else
 	else {
 		__ASSERT(0, "Flash latency not set");