diff --git a/drivers/pinctrl/CMakeLists.txt b/drivers/pinctrl/CMakeLists.txt
index df5cbb1bb7e..c91ed202f57 100644
--- a/drivers/pinctrl/CMakeLists.txt
+++ b/drivers/pinctrl/CMakeLists.txt
@@ -12,3 +12,4 @@ zephyr_library_sources_ifdef(CONFIG_PINCTRL_RPI_PICO pinctrl_rpi_pico.c)
 zephyr_library_sources_ifdef(CONFIG_PINCTRL_STM32 pinctrl_stm32.c)
 zephyr_library_sources_ifdef(CONFIG_PINCTRL_NXP_KINETIS pinctrl_kinetis.c)
 zephyr_library_sources_ifdef(CONFIG_PINCTRL_MCHP_XEC pinctrl_mchp_xec.c)
+zephyr_library_sources_ifdef(CONFIG_PINCTRL_MCUX_RT pinctrl_mcux_rt.c)
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 9c1232a7d88..b0572429c45 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -37,5 +37,6 @@ source "drivers/pinctrl/Kconfig.rpi_pico"
 source "drivers/pinctrl/Kconfig.stm32"
 source "drivers/pinctrl/Kconfig.kinetis"
 source "drivers/pinctrl/Kconfig.xec"
+source "drivers/pinctrl/Kconfig.mcux"
 
 endif # PINCTRL
diff --git a/drivers/pinctrl/Kconfig.mcux b/drivers/pinctrl/Kconfig.mcux
new file mode 100644
index 00000000000..c5a582af572
--- /dev/null
+++ b/drivers/pinctrl/Kconfig.mcux
@@ -0,0 +1,11 @@
+# Copyright (c) 2022 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+DT_COMPAT_MCUX_RT_PINCTRL := nxp,mcux-rt-pinctrl
+
+config PINCTRL_MCUX_RT
+	bool "Pin controller driver for MCUX RT1xxx MCUs"
+	depends on SOC_SERIES_IMX_RT
+	default $(dt_compat_enabled,$(DT_COMPAT_MCUX_RT_PINCTRL))
+	help
+	  Enable pin controller driver for NXP RT series MCUs
diff --git a/drivers/pinctrl/pinctrl_mcux_rt.c b/drivers/pinctrl/pinctrl_mcux_rt.c
new file mode 100644
index 00000000000..a671d08ded6
--- /dev/null
+++ b/drivers/pinctrl/pinctrl_mcux_rt.c
@@ -0,0 +1,48 @@
+/*
+ * Copyright (c) 2022 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define DT_DRV_COMPAT nxp_mcux_rt_pinctrl
+
+#include <drivers/pinctrl.h>
+#include <soc.h>
+#include <fsl_iomuxc.h>
+#include <fsl_gpio.h>
+
+
+int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt,
+			   uintptr_t reg)
+{
+	/* configure all pins */
+	for (uint8_t i = 0U; i < pin_cnt; i++) {
+		uint32_t mux_register = pins[i].pinmux.mux_register;
+		uint32_t mux_mode = pins[i].pinmux.mux_mode;
+		uint32_t input_register = pins[i].pinmux.input_register;
+		uint32_t input_daisy = pins[i].pinmux.input_daisy;
+		uint32_t config_register = pins[i].pinmux.config_register;
+		uint32_t pin_ctrl_flags = pins[i].pin_ctrl_flags;
+
+		IOMUXC_SetPinMux(mux_register, mux_mode, input_register,
+			input_daisy, config_register,
+			MCUX_RT_INPUT_ENABLE(pin_ctrl_flags));
+
+		IOMUXC_SetPinConfig(mux_register, mux_mode, input_register,
+			input_daisy, config_register,
+			pin_ctrl_flags & (~(0x1 << MCUX_RT_INPUT_ENABLE_SHIFT)));
+	}
+	return 0;
+}
+
+static int mcux_pinctrl_init(const struct device *dev)
+{
+	ARG_UNUSED(dev);
+
+	CLOCK_EnableClock(kCLOCK_Iomuxc);
+	CLOCK_EnableClock(kCLOCK_IomuxcSnvs);
+
+	return 0;
+}
+
+SYS_INIT(mcux_pinctrl_init, PRE_KERNEL_1, 0);