diff --git a/boards/silabs/radio_boards/siwx917_rb4338a/siwx917_rb4338a.yaml b/boards/silabs/radio_boards/siwx917_rb4338a/siwx917_rb4338a.yaml index 9b9cddabd8e..4c061ce3515 100644 --- a/boards/silabs/radio_boards/siwx917_rb4338a/siwx917_rb4338a.yaml +++ b/boards/silabs/radio_boards/siwx917_rb4338a/siwx917_rb4338a.yaml @@ -9,6 +9,7 @@ toolchain: - gnuarmemb - xtools supported: + - dma - entropy - gpio - i2c diff --git a/dts/arm/silabs/siwg917.dtsi b/dts/arm/silabs/siwg917.dtsi index 5df283ca1bc..f5c740234f3 100644 --- a/dts/arm/silabs/siwg917.dtsi +++ b/dts/arm/silabs/siwg917.dtsi @@ -216,6 +216,34 @@ clocks = <&clock0 SIWX91X_CLK_I2C1>; status = "disabled"; }; + + dma0: dma@44030000 { + compatible = "silabs,siwx91x-dma"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x44030000 0x82C>; + interrupts = <33 0>; + interrupt-names = "dma0"; + clocks = <&clock0 SIWX91X_CLK_DMA0>; + silabs,sram-desc-addr = <0x2fc00>; + #dma-cells = < 1>; + dma-channels = <32>; + status = "disabled"; + }; + + ulpdma: dma@24078000 { + compatible = "silabs,siwx91x-dma"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x24078000 0x82C>; + interrupts = <10 0>; + interrupt-names = "ulpdma"; + clocks = <&clock0 SIWX91X_CLK_ULP_DMA>; + silabs,sram-desc-addr = <0x24061c00>; + #dma-cells = < 1>; + dma-channels = <12>; + status = "disabled"; + }; }; }; diff --git a/soc/silabs/silabs_siwx91x/siwg917/linker.ld b/soc/silabs/silabs_siwx91x/siwg917/linker.ld index b6e2b16cc91..b21a3cca0ee 100644 --- a/soc/silabs/silabs_siwx91x/siwg917/linker.ld +++ b/soc/silabs/silabs_siwx91x/siwg917/linker.ld @@ -5,10 +5,29 @@ */ #include +MEMORY +{ + udma0 (rwx) : ORIGIN = 0x0002fc00, LENGTH = 0x00000400 + udma1 (rwx) : ORIGIN = 0x24061c00, LENGTH = 0x00000400 +} + SECTIONS { .common_tcm_code : { *(.common_tcm_code*) } > FLASH + + /* These regions of SRAM is where the UDMA descriptors are stored. The corresponding + section must be properly declared in the linker script to ensure correct data transfer + and proper functioning of the UDMA module */ + .udma_addr0 : + { + *(.udma_addr0*) + } > udma0 AT> FLASH + + .udma_addr1 : + { + *(.udma_addr1*) + } > udma1 AT> FLASH }