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riscv: stop preserving the tp register needlessly

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The tp (x4) register is neither caller nor callee saved according to
the RISC-V standard calling convention. It only has to be set on thread
context switching and is otherwise read-only.

To protect the kernel against a possible rogue user thread, the tp is
also re-set on exception entry from u-mode.

Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
This commit is contained in:
Nicolas Pitre 2022-06-07 08:04:55 -04:00 • committed by Anas Nashif
commit 3f8e326d1a
7 changed files with 11 additions and 17 deletions
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9
arch/riscv/core/thread.c
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@ -41,10 +41,6 @@ void arch_new_thread(struct k_thread *thread, k_thread_stack_t *stack,
stack_init->a2 = (ulong_t)p2;
stack_init->a3 = (ulong_t)p3;
#ifdef CONFIG_THREAD_LOCAL_STORAGE
thread->callee_saved.tp = (ulong_t)thread->tls;
#endif
/*
* Following the RISC-V architecture,
* the MSTATUS register (used to globally enable/disable interrupt),
@ -90,11 +86,6 @@ void arch_new_thread(struct k_thread *thread, k_thread_stack_t *stack,
stack_init->sp = (ulong_t)(stack_init + 1);
#endif /* CONFIG_USERSPACE */
#if defined(CONFIG_THREAD_LOCAL_STORAGE)
stack_init->tp = thread->tls;
thread->callee_saved.tp = thread->tls;
#endif
/* Assign thread entry point and mstatus.MPRV mode. */
if (IS_ENABLED(CONFIG_USERSPACE)
&& (thread->base.user_options & K_USER)) {