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riscv: stop preserving the tp register needlessly

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The tp (x4) register is neither caller nor callee saved according to
the RISC-V standard calling convention. It only has to be set on thread
context switching and is otherwise read-only.

To protect the kernel against a possible rogue user thread, the tp is
also re-set on exception entry from u-mode.

Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
This commit is contained in:
Nicolas Pitre 2022-06-07 08:04:55 -04:00 • committed by Anas Nashif
commit 3f8e326d1a
7 changed files with 11 additions and 17 deletions
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7
arch/riscv/core/isr.S
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@ -59,7 +59,6 @@
RV_E( op a5, __z_arch_esf_t_a5_OFFSET(sp) );\
RV_I( op a6, __z_arch_esf_t_a6_OFFSET(sp) );\
RV_I( op a7, __z_arch_esf_t_a7_OFFSET(sp) );\
RV_E( op tp, __z_arch_esf_t_tp_OFFSET(sp) );\
RV_E( op ra, __z_arch_esf_t_ra_OFFSET(sp) )
#ifdef CONFIG_SMP
@ -200,6 +199,12 @@ SECTION_FUNC(exception.entry, _isr_wrapper)
/* save stack value to be restored later */
sr t0, __z_arch_esf_t_sp_OFFSET(sp)
#if defined(CONFIG_THREAD_LOCAL_STORAGE)
/* Make sure tls pointer is sane */
lr t0, ___cpu_t_current_OFFSET(s0)
lr tp, _thread_offset_to_tls(t0)
#endif
#if !defined(CONFIG_SMP)
/* Clear user mode variable */
la t0, is_user_mode