clock_control/stm32f10x: introduce driver for STM32F10x RCC
The patch adds a driver for STM32F10x series RCC (Reset and Clock Control) subsystem. The module is primarily responsible for setting up of MCU's clock tree. In particular the driver sets up SYSCLK, PLL (with source configuration), AHB prescaler, and APB1/APB2 prescalers. As part of this functionality, the subsystem can enable/disable clock signal for particular peripherals, thus reducing the power consumption of the MCU. The driver implements clock control driver API. However, subsystem IDs being HW specific are exposed in driver public header that must be included by callers. The driver registers a single device using a common name STM32_CLOCK_CONTROL_NAME. The device is initialized at the PRIMARY level with priority 1. This allows the initialization to take place right after SoC initialization routine. The driver depends on selection of SOC_STM32F1X config option and is MCU specific. Change-Id: I8bea5db20726a24bce7b7ffe0b95de543240429a Origin: Original Signed-off-by: Maciej Borzecki <maciek.borzecki@gmail.com>
This commit is contained in:
Maciek Borzecki
Daniel Kalowsky
parent
14482f0940
commit
3f5af00529
8 changed files with 600 additions and 0 deletions
118
arch/arm/soc/st_stm32/stm32f1/rcc_registers.h
Normal file
118
arch/arm/soc/st_stm32/stm32f1/rcc_registers.h
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@ -0,0 +1,118 @@
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/*
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* Copyright (c) 2016 Open-RnD Sp. z o.o.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef _STM32F10X_CLOCK_H_
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#define _STM32F10X_CLOCK_H_
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/**
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* @brief Driver for Reset & Clock Control of STM32F10x family processor.
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*
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* Based on reference manual:
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* STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and STM32F107xx
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* advanced ARM ® -based 32-bit MCUs
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*
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* Chapter 7: Low-, medium-, high- and XL-density reset and
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* clock control
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*/
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/* 8.3.1 Clock control register (RCC_CR) */
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enum {
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STM32F10X_RCC_CFG_PLL_SRC_HSI = 0x0,
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STM32F10X_RCC_CFG_PLL_SRC_PREDIV1 = 0x1,
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};
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enum {
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STM32F10X_RCC_CFG_SYSCLK_SRC_HSI = 0x0,
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STM32F10X_RCC_CFG_SYSCLK_SRC_HSE = 0x1,
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STM32F10X_RCC_CFG_SYSCLK_SRC_PLL = 0x2,
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};
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enum {
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STM32F10X_RCC_CFG_HCLK_DIV_0 = 0x0,
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STM32F10X_RCC_CFG_HCLK_DIV_2 = 0x4,
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STM32F10X_RCC_CFG_HCLK_DIV_4 = 0x5,
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STM32F10X_RCC_CFG_HCLK_DIV_8 = 0x6,
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STM32F10X_RCC_CFG_HCLK_DIV_16 = 0x7,
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};
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enum {
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STM32F10X_RCC_CFG_SYSCLK_DIV_0 = 0x0,
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STM32F10X_RCC_CFG_SYSCLK_DIV_2 = 0x8,
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STM32F10X_RCC_CFG_SYSCLK_DIV_4 = 0x9,
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STM32F10X_RCC_CFG_SYSCLK_DIV_8 = 0xa,
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STM32F10X_RCC_CFG_SYSCLK_DIV_16 = 0xb,
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STM32F10X_RCC_CFG_SYSCLK_DIV_64 = 0xc,
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STM32F10X_RCC_CFG_SYSCLK_DIV_128 = 0xd,
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STM32F10X_RCC_CFG_SYSCLK_DIV_256 = 0xe,
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STM32F10X_RCC_CFG_SYSCLK_DIV_512 = 0xf,
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};
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/**
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* @brief Reset and Clock Control
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*/
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union __rcc_cr {
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uint32_t val;
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struct {
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uint32_t hsion :1 __packed;
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uint32_t hsirdy :1 __packed;
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uint32_t rsvd__2 :1 __packed;
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uint32_t hsitrim :5 __packed;
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uint32_t hsical :8 __packed;
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uint32_t hseon :1 __packed;
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uint32_t hserdy :1 __packed;
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uint32_t hsebyp :1 __packed;
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uint32_t csson :1 __packed;
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uint32_t rsvd__20_23 :4 __packed;
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uint32_t pllon :1 __packed;
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uint32_t pllrdy :1 __packed;
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uint32_t rsvd__26_31 :6 __packed;
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} bit;
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};
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union __rcc_cfgr {
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uint32_t val;
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struct {
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uint32_t sw :2 __packed;
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uint32_t sws :2 __packed;
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uint32_t hpre :4 __packed;
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uint32_t ppre1 :3 __packed;
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uint32_t ppre2 :3 __packed;
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uint32_t adcpre :2 __packed;
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uint32_t pllsrc :1 __packed;
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uint32_t pllxtpre :1 __packed;
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uint32_t pllmul :4 __packed;
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uint32_t usbpre :1 __packed;
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uint32_t rsvd__23 :1 __packed;
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uint32_t mco :3 __packed;
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uint32_t rsvd__27_31 :5 __packed;
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} bit;
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};
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struct stm32f10x_rcc {
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union __rcc_cr cr;
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union __rcc_cfgr cfgr;
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uint32_t cir;
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uint32_t apb2rstr;
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uint32_t apb1rstr;
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uint32_t ahbenr;
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uint32_t apb2enr;
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uint32_t apb1enr;
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uint32_t bdcr;
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uint32_t csr;
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};
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#endif /* _STM32F10X_CLOCK_H_ */
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@ -18,5 +18,6 @@
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#define _STM32F10X_SOC_REGISTERS_H_
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#define _STM32F10X_SOC_REGISTERS_H_
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/* include register mapping headers */
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/* include register mapping headers */
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#include "rcc_registers.h"
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#endif /* _STM32F10X_SOC_REGISTERS_H_ */
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#endif /* _STM32F10X_SOC_REGISTERS_H_ */
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@ -39,4 +39,6 @@ config CLOCK_CONTROL_DEBUG
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source "drivers/clock_control/Kconfig.quark_se"
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source "drivers/clock_control/Kconfig.quark_se"
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source "drivers/clock_control/Kconfig.stm32f10x"
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endif # CLOCK_CONTROL
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endif # CLOCK_CONTROL
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112
drivers/clock_control/Kconfig.stm32f10x
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112
drivers/clock_control/Kconfig.stm32f10x
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@ -0,0 +1,112 @@
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# Kconfig - STM32F1 MCU clock control driver config
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#
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# Copyright (c) 2016 Open-RnD Sp. z o.o.
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# You may obtain a copy of the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS,
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# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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# See the License for the specific language governing permissions and
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# limitations under the License.
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#
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if SOC_STM32F1X
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config CLOCK_CONTROL_STM32F10X
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bool
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prompt "STM32F10x Reset & Clock Control"
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depends on CLOCK_CONTROL && SOC_STM32F1X
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default y if SOC_STM32F1X
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help
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Enable driver for Reset & Clock Control subsystem found
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in STM32F1 family of MCUs
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config CLOCK_CONTROL_STM32F10X_DEVICE_PRIORITY
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int "Clock Control Device Priority"
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default 1
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depends on CLOCK_CONTROL_STM32F10X
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help
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This option controls the priority of clock control
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device initialization. Higher priority ensures that the device
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is initialized earlier in the startup cycle. If unsure, leave
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at default value 1
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choice
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prompt "STM32F10x System Clock Source"
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depends on CLOCK_CONTROL_STM32F10X
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config CLOCK_STM32F10X_SYSCLK_SRC_HSI
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bool "HSI"
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help
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Use HSI as source of SYSCLK
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config CLOCK_STM32F10X_SYSCLK_SRC_HSE
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bool "HSE"
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help
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Use HSE as source of SYSCLK
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config CLOCK_STM32F10X_SYSCLK_SRC_PLL
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bool "PLL"
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help
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Use PLL as source of SYSCLK
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endchoice
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choice
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prompt "STM32F10x PLL Clock Source"
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depends on CLOCK_CONTROL_STM32F10X
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config CLOCK_STM32F10X_PLL_SRC_HSI
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bool "HSI"
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help
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Use HSI as source of PLL
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config CLOCK_STM32F10X_PLL_SRC_PREDIV1
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bool "PREDIV1"
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help
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Use PREDIV1 as source of PLL
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endchoice
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config CLOCK_STM32F10X_PLL_MULTIPLIER
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int "PLL multiplier"
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depends on CLOCK_CONTROL_STM32F10X
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default 9
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range 2 16
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help
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PLL multiplier, allowed values: 2-16
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config CLOCK_STM32F10X_AHB_PRESCALER
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int "AHB prescaler"
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depends on CLOCK_CONTROL_STM32F10X
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default 0
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range 0 512
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help
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AHB prescaler, allowed values: 0, 2, 4, 8, 16, 64, 128,
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256, 512.
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config CLOCK_STM32F10X_APB1_PRESCALER
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int "APB1 prescaler"
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depends on CLOCK_CONTROL_STM32F10X
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default 0
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range 0 16
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help
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APB1 Low speed clock (PCLK1) prescaler, allowed values:
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0, 2, 4, 8, 16
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config CLOCK_STM32F10X_APB2_PRESCALER
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int "APB2 prescaler"
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depends on CLOCK_CONTROL_STM32F10X
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default 0
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range 0 16
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help
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APB2 High speed clock (PCLK2) prescaler, allowed values:
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0, 2, 4, 8, 16
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endif
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@ -1 +1,2 @@
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obj-$(CONFIG_CLOCK_CONTROL_QUARK_SE) += quark_se_clock_control.o
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obj-$(CONFIG_CLOCK_CONTROL_QUARK_SE) += quark_se_clock_control.o
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obj-$(CONFIG_CLOCK_CONTROL_STM32F10X) += stm32f10x_clock.o
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276
drivers/clock_control/stm32f10x_clock.c
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276
drivers/clock_control/stm32f10x_clock.c
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@ -0,0 +1,276 @@
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/*
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* Copyright (c) 2016 Open-RnD Sp. z o.o.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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/**
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* @brief Driver for Reset & Clock Control of STM32F10x family processor.
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*
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* Based on reference manual:
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* STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and STM32F107xx
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* advanced ARM ® -based 32-bit MCUs
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*
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* Chapter 7: Low-, medium-, high- and XL-density reset and
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* clock control
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*/
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#include <soc.h>
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#include <soc_registers.h>
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#include <clock_control.h>
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#include <misc/util.h>
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#include <clock_control/stm32_clock_control.h>
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struct stm32f10x_rcc_data {
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uint8_t *base;
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};
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static inline int stm32f10x_clock_control_on(struct device *dev,
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clock_control_subsys_t sub_system)
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{
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struct stm32f10x_rcc_data *data = dev->driver_data;
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volatile struct stm32f10x_rcc *rcc = (struct stm32f10x_rcc *)(data->base);
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uint32_t subsys = POINTER_TO_UINT(sub_system);
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if (subsys > STM32F10X_CLOCK_APB2_BASE) {
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subsys &= ~(STM32F10X_CLOCK_APB2_BASE);
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rcc->apb2enr |= subsys;
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} else {
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rcc->apb1enr |= subsys;
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}
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return DEV_OK;
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}
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static inline int stm32f10x_clock_control_off(struct device *dev,
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clock_control_subsys_t sub_system)
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{
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struct stm32f10x_rcc_data *data = dev->driver_data;
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volatile struct stm32f10x_rcc *rcc =
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(struct stm32f10x_rcc *)(data->base);
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uint32_t subsys = POINTER_TO_UINT(sub_system);
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if (subsys > STM32F10X_CLOCK_APB2_BASE) {
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subsys &= ~(STM32F10X_CLOCK_APB2_BASE);
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rcc->apb2enr &= ~subsys;
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} else {
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rcc->apb1enr &= ~subsys;
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}
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return DEV_OK;
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}
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/**
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* @brief helper for mapping a setting to register value
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*/
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struct regval_map {
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int val;
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int reg;
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};
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int map_reg_val(const struct regval_map *map, size_t cnt, int val)
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{
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for (int i = 0; i < cnt; i++) {
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if (map[i].val == val) {
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return map[i].reg;
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}
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}
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return 0;
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}
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/**
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* @brief map APB prescaler setting to register value
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*/
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static int __apb_prescaler(int prescaler)
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{
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if (prescaler == 0) {
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return STM32F10X_RCC_CFG_HCLK_DIV_0;
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}
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const struct regval_map map[] = {
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{0, STM32F10X_RCC_CFG_HCLK_DIV_0},
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{2, STM32F10X_RCC_CFG_HCLK_DIV_2},
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{4, STM32F10X_RCC_CFG_HCLK_DIV_4},
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||||||
|
{8, STM32F10X_RCC_CFG_HCLK_DIV_8},
|
||||||
|
{16, STM32F10X_RCC_CFG_HCLK_DIV_16},
|
||||||
|
};
|
||||||
|
|
||||||
|
return map_reg_val(map, ARRAY_SIZE(map), prescaler);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief map AHB prescaler setting to register value
|
||||||
|
*/
|
||||||
|
static int __ahb_prescaler(int prescaler)
|
||||||
|
{
|
||||||
|
if (prescaler == 0)
|
||||||
|
return STM32F10X_RCC_CFG_SYSCLK_DIV_0;
|
||||||
|
|
||||||
|
const struct regval_map map[] = {
|
||||||
|
{0, STM32F10X_RCC_CFG_SYSCLK_DIV_0},
|
||||||
|
{2, STM32F10X_RCC_CFG_SYSCLK_DIV_2},
|
||||||
|
{4, STM32F10X_RCC_CFG_SYSCLK_DIV_4},
|
||||||
|
{8, STM32F10X_RCC_CFG_SYSCLK_DIV_8},
|
||||||
|
{16, STM32F10X_RCC_CFG_SYSCLK_DIV_16},
|
||||||
|
{64, STM32F10X_RCC_CFG_SYSCLK_DIV_64},
|
||||||
|
{128, STM32F10X_RCC_CFG_SYSCLK_DIV_128},
|
||||||
|
{256, STM32F10X_RCC_CFG_SYSCLK_DIV_256},
|
||||||
|
{512, STM32F10X_RCC_CFG_SYSCLK_DIV_512},
|
||||||
|
};
|
||||||
|
return map_reg_val(map, ARRAY_SIZE(map), prescaler);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief map PLL multiplier setting to register value
|
||||||
|
*/
|
||||||
|
static int __pllmul(int mul)
|
||||||
|
{
|
||||||
|
/* x2 -> 0x0
|
||||||
|
* x3 -> 0x1
|
||||||
|
* x4 -> 0x2
|
||||||
|
* ...
|
||||||
|
* x15 -> 0xd
|
||||||
|
* x16 -> 0xe
|
||||||
|
* x16 -> 0xf
|
||||||
|
*/
|
||||||
|
return mul - 2;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
uint32_t __get_ahb_clock(uint32_t sysclk)
|
||||||
|
{
|
||||||
|
/* AHB clock is generated based on SYSCLK */
|
||||||
|
uint32_t sysclk_div = CONFIG_CLOCK_STM32F10X_AHB_PRESCALER;
|
||||||
|
|
||||||
|
if (sysclk_div == 0) {
|
||||||
|
sysclk_div = 1;
|
||||||
|
}
|
||||||
|
return sysclk / sysclk_div;
|
||||||
|
}
|
||||||
|
|
||||||
|
uint32_t __get_apb_clock(uint32_t ahb_clock, uint32_t prescaler)
|
||||||
|
{
|
||||||
|
if (prescaler == 0) {
|
||||||
|
prescaler = 1;
|
||||||
|
}
|
||||||
|
return ahb_clock / prescaler;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int stm32f10x_clock_control_get_subsys_rate(struct device *clock,
|
||||||
|
clock_control_subsys_t sub_system,
|
||||||
|
uint32_t *rate)
|
||||||
|
{
|
||||||
|
ARG_UNUSED(clock);
|
||||||
|
|
||||||
|
uint32_t subsys = POINTER_TO_UINT(sub_system);
|
||||||
|
|
||||||
|
uint32_t prescaler = CONFIG_CLOCK_STM32F10X_APB1_PRESCALER;
|
||||||
|
|
||||||
|
if (subsys > STM32F10X_CLOCK_APB2_BASE) {
|
||||||
|
prescaler = CONFIG_CLOCK_STM32F10X_APB2_PRESCALER;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* assumes SYSCLK is SYS_CLOCK_HW_CYCLES_PER_SEC */
|
||||||
|
uint32_t ahb_clock =
|
||||||
|
__get_ahb_clock(CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC);
|
||||||
|
|
||||||
|
*rate = __get_apb_clock(ahb_clock, prescaler);
|
||||||
|
|
||||||
|
return DEV_OK;
|
||||||
|
}
|
||||||
|
|
||||||
|
static struct clock_control_driver_api stm32f10x_clock_control_api = {
|
||||||
|
.on = stm32f10x_clock_control_on,
|
||||||
|
.off = stm32f10x_clock_control_off,
|
||||||
|
.get_rate = stm32f10x_clock_control_get_subsys_rate,
|
||||||
|
};
|
||||||
|
|
||||||
|
int stm32f10x_clock_control_init(struct device *dev)
|
||||||
|
{
|
||||||
|
struct stm32f10x_rcc_data *data = dev->driver_data;
|
||||||
|
volatile struct stm32f10x_rcc *rcc =
|
||||||
|
(struct stm32f10x_rcc *)(data->base);
|
||||||
|
|
||||||
|
/* enable HSI clock */
|
||||||
|
rcc->cr.bit.hsion = 1;
|
||||||
|
/* this should end after one test */
|
||||||
|
while (rcc->cr.bit.hsirdy != 1) {
|
||||||
|
}
|
||||||
|
|
||||||
|
/* disable PLL */
|
||||||
|
rcc->cr.bit.pllon = 0;
|
||||||
|
|
||||||
|
#ifdef CONFIG_CLOCK_STM32F10X_PLL_SRC_HSI
|
||||||
|
/* PLL input from HSI/2 = 4MHz */
|
||||||
|
rcc->cfgr.bit.pllsrc = STM32F10X_RCC_CFG_PLL_SRC_HSI;
|
||||||
|
#elif defined(CONFIG_CLOCK_STM32F10X_PLL_SRC_PREDIV1)
|
||||||
|
#error PREDIV1 as PLL source is not supported
|
||||||
|
rcc->cfgr.bit.pllsrc = STM32F10X_RCC_CFG_PLL_SRC_PREDIV1;
|
||||||
|
#endif
|
||||||
|
|
||||||
|
uint32_t pllmul = __pllmul(CONFIG_CLOCK_STM32F10X_PLL_MULTIPLIER);
|
||||||
|
/* setup PLL multiplication (PLL must be disabled) */
|
||||||
|
rcc->cfgr.bit.pllmul = pllmul;
|
||||||
|
|
||||||
|
/* enable PLL */
|
||||||
|
rcc->cr.bit.pllon = 1;
|
||||||
|
|
||||||
|
/* wait for PLL to become ready */
|
||||||
|
while (rcc->cr.bit.pllrdy != 1) {
|
||||||
|
}
|
||||||
|
|
||||||
|
uint32_t hpre = __ahb_prescaler(CONFIG_CLOCK_STM32F10X_AHB_PRESCALER);
|
||||||
|
/* setup AHB prescaler */
|
||||||
|
rcc->cfgr.bit.hpre = hpre;
|
||||||
|
|
||||||
|
uint32_t ppre1 = __apb_prescaler(CONFIG_CLOCK_STM32F10X_APB1_PRESCALER);
|
||||||
|
/* setup APB1, must not exceed 36MHz, prescaler set to 0 */
|
||||||
|
rcc->cfgr.bit.ppre1 = ppre1;
|
||||||
|
|
||||||
|
uint32_t ppre2 = __apb_prescaler(CONFIG_CLOCK_STM32F10X_APB2_PRESCALER);
|
||||||
|
/* setup APB2 to use 36MHz, prescaler set to 0 */
|
||||||
|
rcc->cfgr.bit.ppre2 = ppre2;
|
||||||
|
|
||||||
|
/* setup SYSCLK source, default to HSI */
|
||||||
|
int sysclk_src = STM32F10X_RCC_CFG_SYSCLK_SRC_HSI;
|
||||||
|
#ifdef CONFIG_CLOCK_STM32F10X_SYSCLK_SRC_PLL
|
||||||
|
sysclk_src = STM32F10X_RCC_CFG_SYSCLK_SRC_PLL;
|
||||||
|
#elif defined(CONFIG_CLOCK_STM32F10X_SYSCLK_SRC_HSE)
|
||||||
|
sysclk_src = STM32F10X_RCC_CFG_SYSCLK_SRC_HSE;
|
||||||
|
#endif
|
||||||
|
/* set SYSCLK clock value */
|
||||||
|
rcc->cfgr.bit.sw = sysclk_src;
|
||||||
|
|
||||||
|
/* wait for SYSCLK to switch the source */
|
||||||
|
while (rcc->cfgr.bit.sws != sysclk_src) {
|
||||||
|
}
|
||||||
|
|
||||||
|
dev->driver_api = &stm32f10x_clock_control_api;
|
||||||
|
return DEV_OK;
|
||||||
|
}
|
||||||
|
|
||||||
|
static struct stm32f10x_rcc_data stm32f10x_rcc_data = {
|
||||||
|
.base = (uint8_t *)RCC_BASE,
|
||||||
|
};
|
||||||
|
|
||||||
|
/* FIXME: move prescaler/multiplier defines into device config */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief RCC device, note that priority is intentionally set to 1 so
|
||||||
|
* that the device init runs just after SOC init
|
||||||
|
*/
|
||||||
|
DEVICE_INIT(rcc_stm32f10x, STM32_CLOCK_CONTROL_NAME,
|
||||||
|
&stm32f10x_clock_control_init,
|
||||||
|
&stm32f10x_rcc_data, NULL,
|
||||||
|
PRIMARY, CONFIG_CLOCK_CONTROL_STM32F10X_DEVICE_PRIORITY);
|
||||||
28
include/drivers/clock_control/stm32_clock_control.h
Normal file
28
include/drivers/clock_control/stm32_clock_control.h
Normal file
|
|
@ -0,0 +1,28 @@
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2016 Open-RnD Sp. z o.o.
|
||||||
|
*
|
||||||
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||||
|
* you may not use this file except in compliance with the License.
|
||||||
|
* You may obtain a copy of the License at
|
||||||
|
*
|
||||||
|
* http://www.apache.org/licenses/LICENSE-2.0
|
||||||
|
*
|
||||||
|
* Unless required by applicable law or agreed to in writing, software
|
||||||
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||||
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
* See the License for the specific language governing permissions and
|
||||||
|
* limitations under the License.
|
||||||
|
*/
|
||||||
|
#ifndef _STM32_CLOCK_CONTROL_H_
|
||||||
|
#define _STM32_CLOCK_CONTROL_H_
|
||||||
|
|
||||||
|
#include <clock_control.h>
|
||||||
|
|
||||||
|
/* common clock control device name for all STM32 chips */
|
||||||
|
#define STM32_CLOCK_CONTROL_NAME "stm32-cc"
|
||||||
|
|
||||||
|
#ifdef CONFIG_SOC_STM32F1X
|
||||||
|
#include "stm32f1_clock_control.h"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* _STM32_CLOCK_CONTROL_H_ */
|
||||||
62
include/drivers/clock_control/stm32f1_clock_control.h
Normal file
62
include/drivers/clock_control/stm32f1_clock_control.h
Normal file
|
|
@ -0,0 +1,62 @@
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2016 Open-RnD Sp. z o.o.
|
||||||
|
*
|
||||||
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||||
|
* you may not use this file except in compliance with the License.
|
||||||
|
* You may obtain a copy of the License at
|
||||||
|
*
|
||||||
|
* http://www.apache.org/licenses/LICENSE-2.0
|
||||||
|
*
|
||||||
|
* Unless required by applicable law or agreed to in writing, software
|
||||||
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||||
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
* See the License for the specific language governing permissions and
|
||||||
|
* limitations under the License.
|
||||||
|
*/
|
||||||
|
#ifndef _STM32F1_CLOCK_CONTROL_H_
|
||||||
|
#define _STM32F1_CLOCK_CONTROL_H_
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @file clock subsystem IDs for STM32F1 family
|
||||||
|
*/
|
||||||
|
|
||||||
|
enum {
|
||||||
|
/* APB1 */
|
||||||
|
STM32F10X_CLOCK_SUBSYS_TIM2 = 1 << 0,
|
||||||
|
STM32F10X_CLOCK_SUBSYS_TIM3 = 1 << 1,
|
||||||
|
STM32F10X_CLOCK_SUBSYS_TIM4 = 1 << 2,
|
||||||
|
STM32F10X_CLOCK_SUBSYS_TIM5 = 1 << 3,
|
||||||
|
STM32F10X_CLOCK_SUBSYS_TIM6 = 1 << 4,
|
||||||
|
STM32F10X_CLOCK_SUBSYS_TIM7 = 1 << 5,
|
||||||
|
STM32F10X_CLOCK_SUBSYS_WWDG = 1 << 11,
|
||||||
|
STM32F10X_CLOCK_SUBSYS_SPI2 = 1 << 14,
|
||||||
|
STM32F10X_CLOCK_SUBSYS_SPI3 = 1 << 15,
|
||||||
|
STM32F10X_CLOCK_SUBSYS_USART2 = 1 << 17,
|
||||||
|
STM32F10X_CLOCK_SUBSYS_USART3 = 1 << 18,
|
||||||
|
STM32F10X_CLOCK_SUBSYS_UART4 = 1 << 19,
|
||||||
|
STM32F10X_CLOCK_SUBSYS_UART5 = 1 << 20,
|
||||||
|
STM32F10X_CLOCK_SUBSYS_I2C1 = 1 << 21,
|
||||||
|
STM32F10X_CLOCK_SUBSYS_I2C2 = 1 << 22,
|
||||||
|
STM32F10X_CLOCK_SUBSYS_CAN1 = 1 << 25,
|
||||||
|
STM32F10X_CLOCK_SUBSYS_CAN2 = 1 << 26,
|
||||||
|
STM32F10X_CLOCK_SUBSYS_BKP = 1 << 27,
|
||||||
|
STM32F10X_CLOCK_SUBSYS_PWR = 1 << 28,
|
||||||
|
STM32F10X_CLOCK_SUBSYS_DAC = 1 << 29,
|
||||||
|
|
||||||
|
STM32F10X_CLOCK_APB2_BASE = 1 << 31,
|
||||||
|
/* APB2 */
|
||||||
|
STM32F10X_CLOCK_SUBSYS_AFIO = STM32F10X_CLOCK_APB2_BASE | 1 << 0,
|
||||||
|
STM32F10X_CLOCK_SUBSYS_IOPA = STM32F10X_CLOCK_APB2_BASE | 1 << 2,
|
||||||
|
STM32F10X_CLOCK_SUBSYS_IOPB = STM32F10X_CLOCK_APB2_BASE | 1 << 3,
|
||||||
|
STM32F10X_CLOCK_SUBSYS_IOPC = STM32F10X_CLOCK_APB2_BASE | 1 << 4,
|
||||||
|
STM32F10X_CLOCK_SUBSYS_IOPD = STM32F10X_CLOCK_APB2_BASE | 1 << 5,
|
||||||
|
STM32F10X_CLOCK_SUBSYS_IOPE = STM32F10X_CLOCK_APB2_BASE | 1 << 6,
|
||||||
|
STM32F10X_CLOCK_SUBSYS_ADC1 = STM32F10X_CLOCK_APB2_BASE | 1 << 9,
|
||||||
|
STM32F10X_CLOCK_SUBSYS_ADC2 = STM32F10X_CLOCK_APB2_BASE | 1 << 10,
|
||||||
|
STM32F10X_CLOCK_SUBSYS_TIM1 = STM32F10X_CLOCK_APB2_BASE | 1 << 11,
|
||||||
|
STM32F10X_CLOCK_SUBSYS_SPI1 = STM32F10X_CLOCK_APB2_BASE | 1 << 12,
|
||||||
|
STM32F10X_CLOCK_SUBSYS_USART1 = STM32F10X_CLOCK_APB2_BASE | 1 << 14,
|
||||||
|
|
||||||
|
};
|
||||||
|
|
||||||
|
#endif /* _STM32F1_CLOCK_CONTROL_H_ */
|
||||||
Loading…
Add table
Add a link
Reference in a new issue