boards: nucleo_h723zg: Enable SPI

Enable SPI on nucleo_h723zg board

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This commit is contained in:
Erwan Gouriou 2022-01-24 16:37:47 +01:00 committed by Carles Cufí
commit 3f503e87cc
5 changed files with 32 additions and 1 deletions

View file

@ -35,5 +35,5 @@
}; };
arduino_i2c: &i2c1 {}; arduino_i2c: &i2c1 {};
arduino_spi: &spi1 {};
arduino_serial: &uart8 {}; arduino_serial: &uart8 {};

View file

@ -107,6 +107,8 @@ features:
+-------------+------------+-------------------------------------+ +-------------+------------+-------------------------------------+
| I2C | on-chip | i2c | | I2C | on-chip | i2c |
+-------------+------------+-------------------------------------+ +-------------+------------+-------------------------------------+
| SPI | on-chip | spi |
+-------------+------------+-------------------------------------+
| PWM | on-chip | pwm | | PWM | on-chip | pwm |
+-------------+------------+-------------------------------------+ +-------------+------------+-------------------------------------+
| ETHERNET | on-chip | ethernet | | ETHERNET | on-chip | ethernet |
@ -135,6 +137,7 @@ and a ST morpho connector. Board is configured as follows:
- LD2 : PB7 - LD2 : PB7
- LD3 : PB14 - LD3 : PB14
- I2C : PB8, PB9 - I2C : PB8, PB9
- SPI1 NSS/SCK/MISO/MOSI : PD14PA5/PA6/PB5 (Arduino SPI)
System Clock System Clock
------------ ------------

View file

@ -115,6 +115,13 @@
status = "okay"; status = "okay";
}; };
&spi1 {
status = "okay";
pinctrl-0 = <&spi1_sck_pa5 &spi1_miso_pa6 &spi1_mosi_pb5>;
pinctrl-names = "default";
cs-gpios = <&gpiod 14 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
};
&i2c1 { &i2c1 {
pinctrl-0 = <&i2c1_scl_pb8 &i2c1_sda_pb9>; pinctrl-0 = <&i2c1_scl_pb8 &i2c1_sda_pb9>;
pinctrl-names = "default"; pinctrl-names = "default";

View file

@ -11,10 +11,12 @@ flash: 1024
supported: supported:
- arduino_gpio - arduino_gpio
- arduino_i2c - arduino_i2c
- arduino_spi
- uart - uart
- gpio - gpio
- counter - counter
- i2c - i2c
- pwm - pwm
- spi
- netif:eth - netif:eth
- backup_sram - backup_sram

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@ -0,0 +1,19 @@
/*
* Copyright (c) 2021 STMicroelectronics
*
* SPDX-License-Identifier: Apache-2.0
*/
/* Set div-q to get test clk freq into acceptable SPI freq range */
&pll {
/delete-property/ div-q;
div-q = <8>;
};
/* Define PLL1_Q as SPI1 kernel clock source */
&spi1 {
/delete-property/ clocks;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00001000>,
<&rcc STM32_SRC_PLL1_Q SPI123_SEL(0)>;
clock-names = "reg", "kernel";
};