michaelh/zephyr
1
0
Fork 0
Code Releases Activity

dts: nxp: kinetis: Update nxp,kinetis-gpio binding for port connection

Browse source 
Add a property to the nxp,kinetis-gpio binding that related the GPIO
node to the pinmux PORT node.

For the kl25z we add the pinmux nodes as well since they didn't exist.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This commit is contained in:
Kumar Gala 2020-02-12 13:06:04 -06:00 • committed by Maureen Helm
commit 3f2bee6013
10 changed files with 78 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

5
dts/arm/nxp/nxp_k2x.dtsi
View file

@ -233,6 +233,7 @@
label = "GPIO_0";
gpio-controller;
#gpio-cells = <2>;
nxp,kinetis-port = <&pinmux_a>;
};
gpiob: gpio@400ff040 {
@ -242,6 +243,7 @@
label = "GPIO_1";
gpio-controller;
#gpio-cells = <2>;
nxp,kinetis-port = <&pinmux_b>;
};
gpioc: gpio@400ff080 {
@ -251,6 +253,7 @@
label = "GPIO_2";
gpio-controller;
#gpio-cells = <2>;
nxp,kinetis-port = <&pinmux_c>;
};
gpiod: gpio@400ff0c0 {
@ -260,6 +263,7 @@
label = "GPIO_3";
gpio-controller;
#gpio-cells = <2>;
nxp,kinetis-port = <&pinmux_d>;
};
gpioe: gpio@400ff100 {
@ -269,6 +273,7 @@
label = "GPIO_4";
gpio-controller;
#gpio-cells = <2>;
nxp,kinetis-port = <&pinmux_e>;
};
spi0: spi@4002c000 {

5
dts/arm/nxp/nxp_k6x.dtsi
View file

@ -296,6 +296,7 @@
label = "GPIO_0";
gpio-controller;
#gpio-cells = <2>;
nxp,kinetis-port = <&pinmux_a>;
};
gpiob: gpio@400ff040 {
@ -305,6 +306,7 @@
label = "GPIO_1";
gpio-controller;
#gpio-cells = <2>;
nxp,kinetis-port = <&pinmux_b>;
};
gpioc: gpio@400ff080 {
@ -314,6 +316,7 @@
label = "GPIO_2";
gpio-controller;
#gpio-cells = <2>;
nxp,kinetis-port = <&pinmux_c>;
};
gpiod: gpio@400ff0c0 {
@ -323,6 +326,7 @@
label = "GPIO_3";
gpio-controller;
#gpio-cells = <2>;
nxp,kinetis-port = <&pinmux_d>;
};
gpioe: gpio@400ff100 {
@ -332,6 +336,7 @@
label = "GPIO_4";
gpio-controller;
#gpio-cells = <2>;
nxp,kinetis-port = <&pinmux_e>;
};
spi0: spi@4002c000 {

5
dts/arm/nxp/nxp_k8x.dtsi
View file

@ -107,6 +107,7 @@
label = "GPIO_0";
gpio-controller;
#gpio-cells = <2>;
nxp,kinetis-port = <&pinmux_a>;
};
gpiob: gpio@400ff040 {
@ -116,6 +117,7 @@
label = "GPIO_1";
gpio-controller;
#gpio-cells = <2>;
nxp,kinetis-port = <&pinmux_b>;
};
gpioc: gpio@400ff080 {
@ -125,6 +127,7 @@
label = "GPIO_2";
gpio-controller;
#gpio-cells = <2>;
nxp,kinetis-port = <&pinmux_c>;
};
gpiod: gpio@400ff0c0 {
@ -134,6 +137,7 @@
label = "GPIO_3";
gpio-controller;
#gpio-cells = <2>;
nxp,kinetis-port = <&pinmux_d>;
};
gpioe: gpio@400ff100 {
@ -143,6 +147,7 @@
label = "GPIO_4";
gpio-controller;
#gpio-cells = <2>;
nxp,kinetis-port = <&pinmux_e>;
};
i2c0: i2c@40066000 {

5
dts/arm/nxp/nxp_ke1xf.dtsi
View file

@ -305,6 +305,7 @@
label = "GPIO_0";
gpio-controller;
#gpio-cells = <2>;
nxp,kinetis-port = <&pinmux_a>;
};
gpiob: gpio@400ff040 {
@ -314,6 +315,7 @@
label = "GPIO_1";
gpio-controller;
#gpio-cells = <2>;
nxp,kinetis-port = <&pinmux_b>;
};
gpioc: gpio@400ff080 {
@ -323,6 +325,7 @@
label = "GPIO_2";
gpio-controller;
#gpio-cells = <2>;
nxp,kinetis-port = <&pinmux_c>;
};
gpiod: gpio@400ff0c0 {
@ -332,6 +335,7 @@
label = "GPIO_3";
gpio-controller;
#gpio-cells = <2>;
nxp,kinetis-port = <&pinmux_d>;
};
gpioe: gpio@400ff100 {
@ -341,6 +345,7 @@
label = "GPIO_4";
gpio-controller;
#gpio-cells = <2>;
nxp,kinetis-port = <&pinmux_e>;
};
adc0: adc@4003b000 {

35
dts/arm/nxp/nxp_kl25z.dtsi
View file

@ -105,6 +105,36 @@
#io-channel-cells = <1>;
};
pinmux_a: pinmux@40049000 {
compatible = "nxp,kinetis-pinmux";
reg = <0x40049000 0xd0>;
clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 9>;
};
pinmux_b: pinmux@4004a000 {
compatible = "nxp,kinetis-pinmux";
reg = <0x4004a000 0xd0>;
clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 10>;
};
pinmux_c: pinmux@4004b000 {
compatible = "nxp,kinetis-pinmux";
reg = <0x4004b000 0xd0>;
clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 11>;
};
pinmux_d: pinmux@4004c000 {
compatible = "nxp,kinetis-pinmux";
reg = <0x4004c000 0xd0>;
clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 12>;
};
pinmux_e: pinmux@4004d000 {
compatible = "nxp,kinetis-pinmux";
reg = <0x4004d000 0xd0>;
clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 13>;
};
gpioa: gpio@400ff000 {
compatible = "nxp,kinetis-gpio";
reg = <0x400ff000 0x40>;
@ -112,6 +142,7 @@
label = "GPIO_0";
gpio-controller;
#gpio-cells = <2>;
nxp,kinetis-port = <&pinmux_a>;
};
gpiob: gpio@400ff040 {
@ -120,6 +151,7 @@
label = "GPIO_1";
gpio-controller;
#gpio-cells = <2>;
nxp,kinetis-port = <&pinmux_b>;
};
gpioc: gpio@400ff080 {
@ -128,6 +160,7 @@
label = "GPIO_2";
gpio-controller;
#gpio-cells = <2>;
nxp,kinetis-port = <&pinmux_c>;
};
gpiod: gpio@400ff0c0 {
@ -137,6 +170,7 @@
label = "GPIO_3";
gpio-controller;
#gpio-cells = <2>;
nxp,kinetis-port = <&pinmux_d>;
};
gpioe: gpio@400ff100 {
@ -145,6 +179,7 @@
label = "GPIO_4";
gpio-controller;
#gpio-cells = <2>;
nxp,kinetis-port = <&pinmux_e>;
};
usbd: usbd@40072000 {

5
dts/arm/nxp/nxp_kv5x.dtsi
View file

@ -102,6 +102,7 @@
label = "GPIO_0";
gpio-controller;
#gpio-cells = <2>;
nxp,kinetis-port = <&pinmux_a>;
};
gpiob: gpio@400ff040 {
@ -111,6 +112,7 @@
label = "GPIO_1";
gpio-controller;
#gpio-cells = <2>;
nxp,kinetis-port = <&pinmux_b>;
};
gpioc: gpio@400ff080 {
@ -120,6 +122,7 @@
label = "GPIO_2";
gpio-controller;
#gpio-cells = <2>;
nxp,kinetis-port = <&pinmux_c>;
};
gpiod: gpio@400ff0c0 {
@ -129,6 +132,7 @@
label = "GPIO_3";
gpio-controller;
#gpio-cells = <2>;
nxp,kinetis-port = <&pinmux_d>;
};
gpioe: gpio@400ff100 {
@ -138,6 +142,7 @@
label = "GPIO_4";
gpio-controller;
#gpio-cells = <2>;
nxp,kinetis-port = <&pinmux_e>;
};
i2c0: i2c@40066000 {

5
dts/arm/nxp/nxp_kw2xd.dtsi
View file

@ -192,6 +192,7 @@
label = "GPIO_0";
gpio-controller;
#gpio-cells = <2>;
nxp,kinetis-port = <&pinmux_a>;
};
gpiob: gpio@400ff040 {
@ -201,6 +202,7 @@
label = "GPIO_1";
gpio-controller;
#gpio-cells = <2>;
nxp,kinetis-port = <&pinmux_b>;
};
gpioc: gpio@400ff080 {
@ -210,6 +212,7 @@
label = "GPIO_2";
gpio-controller;
#gpio-cells = <2>;
nxp,kinetis-port = <&pinmux_c>;
};
gpiod: gpio@400ff0c0 {
@ -219,6 +222,7 @@
label = "GPIO_3";
gpio-controller;
#gpio-cells = <2>;
nxp,kinetis-port = <&pinmux_d>;
};
gpioe: gpio@400ff100 {
@ -228,6 +232,7 @@
label = "GPIO_4";
gpio-controller;
#gpio-cells = <2>;
nxp,kinetis-port = <&pinmux_e>;
};
spi0: spi@4002c000 {

3
dts/arm/nxp/nxp_kw40z.dtsi
View file

@ -143,6 +143,7 @@
label = "GPIO_0";
gpio-controller;
#gpio-cells = <2>;
nxp,kinetis-port = <&pinmux_a>;
};
gpiob: gpio@400ff040 {
@ -151,6 +152,7 @@
label = "GPIO_2";
gpio-controller;
#gpio-cells = <2>;
nxp,kinetis-port = <&pinmux_b>;
};
gpioc: gpio@400ff080 {
@ -160,6 +162,7 @@
label = "GPIO_3";
gpio-controller;
#gpio-cells = <2>;
nxp,kinetis-port = <&pinmux_c>;
};
spi0: spi@4002c000 {

3
dts/arm/nxp/nxp_kw41z.dtsi
View file

@ -146,6 +146,7 @@
label = "GPIO_0";
gpio-controller;
#gpio-cells = <2>;
nxp,kinetis-port = <&pinmux_a>;
};
gpiob: gpio@400ff040 {
@ -154,6 +155,7 @@
label = "GPIO_1";
gpio-controller;
#gpio-cells = <2>;
nxp,kinetis-port = <&pinmux_b>;
};
gpioc: gpio@400ff080 {
@ -163,6 +165,7 @@
label = "GPIO_2";
gpio-controller;
#gpio-cells = <2>;
nxp,kinetis-port = <&pinmux_c>;
};
spi0: spi@4002c000 {

7
dts/bindings/gpio/nxp,kinetis-gpio.yaml
View file

@ -14,6 +14,13 @@ properties:
"#gpio-cells":
const: 2
nxp,kinetis-port:
required: true
type: phandle
description: |
A phandle reference to the device tree node that contains the pinmux
port associated with this GPIO controller.
gpio-cells:
- pin
- flags