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drivers: mcr20a: allow use the driver with KW2xD devices

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This patch allows the use of the MCR20A driver with KW2xD devices.
The clock output of the transceiver can be used as an input clock
for the PLL of the SoC. The hardware reset and CLK_OUT setup of
the transceiver should then be performed during the initialization
of the SoC. The driver is not allowed to do it again.

Signed-off-by: Johann Fischer <j.fischer@phytec.de>
This commit is contained in:
Johann Fischer 2017-07-21 18:51:35 +02:00 • committed by Jukka Rissanen
commit 3f05300924
2 changed files with 39 additions and 14 deletions
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9
drivers/ieee802154/Kconfig.mcr20a
View file

@ -64,8 +64,17 @@ config MCR20A_GPIO_RESET_PIN
int "GPIO pin connected to RESET input of MCR20A" int "GPIO pin connected to RESET input of MCR20A"
default 2 default 2
config MCR20A_IS_PART_OF_KW2XD_SIP
bool "MCR20A device is part of KW2xD SiP"
default n
help
If this option is set, the driver does not perform a hardware
reset and the CLK_OUT frequency is not set, instead these settings
are performed during the initialization of the SoC.
choice choice
prompt "CLK_OUT frequency" prompt "CLK_OUT frequency"
default MCR20A_CLK_OUT_4MHZ if MCR20A_IS_PART_OF_KW2XD_SIP
default MCR20A_CLK_OUT_DISABLED default MCR20A_CLK_OUT_DISABLED
help help
Configuration of the MCR20A clock output pin. Configuration of the MCR20A clock output pin.

44
drivers/ieee802154/ieee802154_mcr20a.c
View file

@ -88,6 +88,12 @@
#endif #endif
#ifdef CONFIG_MCR20A_IS_PART_OF_KW2XD_SIP
#define PART_OF_KW2XD_SIP 1
#else
#define PART_OF_KW2XD_SIP 0
#endif
/* Values for the power mode (PM) configuration */ /* Values for the power mode (PM) configuration */
#define MCR20A_PM_HIBERNATE 0 #define MCR20A_PM_HIBERNATE 0
#define MCR20A_PM_DOZE MCR20A_PWR_MODES_XTALEN #define MCR20A_PM_DOZE MCR20A_PWR_MODES_XTALEN
@ -1188,6 +1194,7 @@ error:
static int mcr20a_stop(struct device *dev) static int mcr20a_stop(struct device *dev)
{ {
struct mcr20a_context *mcr20a = dev->driver_data; struct mcr20a_context *mcr20a = dev->driver_data;
u8_t power_mode;
k_mutex_lock(&mcr20a->phy_mutex, K_FOREVER); k_mutex_lock(&mcr20a->phy_mutex, K_FOREVER);
@ -1203,7 +1210,13 @@ static int mcr20a_stop(struct device *dev)
enable_irqb_interrupt(mcr20a, false); enable_irqb_interrupt(mcr20a, false);
if (!write_reg_pwr_modes(&mcr20a->spi, MCR20A_PM_HIBERNATE)) { if (PART_OF_KW2XD_SIP) {
power_mode = MCR20A_PM_DOZE;
} else {
power_mode = MCR20A_PM_HIBERNATE;
}
if (!write_reg_pwr_modes(&mcr20a->spi, power_mode)) {
goto error; goto error;
} }
@ -1268,20 +1281,23 @@ static int power_on_and_setup(struct device *dev)
u32_t status; u32_t status;
u8_t tmp = 0; u8_t tmp = 0;
set_reset(dev, 0); if (!PART_OF_KW2XD_SIP) {
_usleep(150); set_reset(dev, 0);
set_reset(dev, 1); _usleep(150);
set_reset(dev, 1);
do { do {
_usleep(50); _usleep(50);
timeout--; timeout--;
gpio_pin_read(mcr20a->irq_gpio, gpio_pin_read(mcr20a->irq_gpio,
CONFIG_MCR20A_GPIO_IRQ_B_PIN, &status); CONFIG_MCR20A_GPIO_IRQ_B_PIN, &status);
} while (status && timeout); } while (status && timeout);
if (status) {
SYS_LOG_ERR("Timeout, failed to get WAKE IRQ");
return -EIO;
}
if (status) {
SYS_LOG_ERR("Timeout, failed to get WAKE IRQ");
return -EIO;
} }
tmp = MCR20A_CLK_OUT_CONFIG | MCR20A_CLK_OUT_EXTEND; tmp = MCR20A_CLK_OUT_CONFIG | MCR20A_CLK_OUT_EXTEND;
@ -1352,7 +1368,7 @@ static inline int configure_gpios(struct device *dev)
gpio_pin_configure(mcr20a->reset_gpio, CONFIG_MCR20A_GPIO_RESET_PIN, gpio_pin_configure(mcr20a->reset_gpio, CONFIG_MCR20A_GPIO_RESET_PIN,
GPIO_DIR_OUT); GPIO_DIR_OUT);
set_reset(dev, 0); set_reset(dev, 1);
return 0; return 0;
} }