diff --git a/include/arch/xtensa/addr_types.h b/include/arch/xtensa/addr_types.h
new file mode 100644
index 00000000000..8eaadc5b3fc
--- /dev/null
+++ b/include/arch/xtensa/addr_types.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright (c) 2016 Cadence Design Systems, Inc.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef XTENSA_ADDR_TYPES_H
+#define XTENSA_ADDR_TYPES_H
+
+#ifndef _ASMLANGUAGE
+typedef unsigned int paddr_t;
+typedef unsigned int vaddr_t;
+#endif
+
+#endif /* XTENSA_ADDR_TYPES_H */
+
diff --git a/include/arch/xtensa/offsets.h b/include/arch/xtensa/offsets.h
new file mode 100644
index 00000000000..4dbc4061301
--- /dev/null
+++ b/include/arch/xtensa/offsets.h
@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2016 Cadence Design Systems, Inc.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef OFFSETS_H
+#define OFFSETS_H
+
+
+
+#endif /* OFFSETS_H */
diff --git a/include/arch/xtensa/xtensa_irq.h b/include/arch/xtensa/xtensa_irq.h
new file mode 100644
index 00000000000..aaf612b1ce9
--- /dev/null
+++ b/include/arch/xtensa/xtensa_irq.h
@@ -0,0 +1,66 @@
+/*
+ * Copyright (c) 2016 Cadence Design Systems, Inc.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef XTENSA_IRQ_H
+#define XTENSA_IRQ_H
+
+#include <xtensa_api.h>
+#include <xtensa/xtruntime.h>
+
+/**
+ *
+ * @brief Enable an interrupt line
+ *
+ * Clear possible pending interrupts on the line, and enable the interrupt
+ * line. After this call, the CPU will receive interrupts for the specified
+ * IRQ.
+ *
+ * @return N/A
+ */
+static ALWAYS_INLINE void _arch_irq_enable(uint32_t irq)
+{
+	_xt_ints_on(1 << irq);
+}
+
+/**
+ *
+ * @brief Disable an interrupt line
+ *
+ * Disable an interrupt line. After this call, the CPU will stop receiving
+ * interrupts for the specified IRQ.
+ *
+ * @return N/A
+ */
+static ALWAYS_INLINE void _arch_irq_disable(uint32_t irq)
+{
+	_xt_ints_off(1 << irq);
+}
+
+static ALWAYS_INLINE unsigned int _arch_irq_lock(void)
+{
+	unsigned int key = XTOS_SET_INTLEVEL(XCHAL_EXCM_LEVEL);
+	return key;
+}
+
+static ALWAYS_INLINE void _arch_irq_unlock(unsigned int key)
+{
+	XTOS_RESTORE_INTLEVEL(key);
+}
+
+#include <irq.h>
+
+#endif /* XTENSA_IRQ_H */
diff --git a/include/arch/xtensa/xtensa_sys_io.h b/include/arch/xtensa/xtensa_sys_io.h
new file mode 100644
index 00000000000..36f516e6b70
--- /dev/null
+++ b/include/arch/xtensa/xtensa_sys_io.h
@@ -0,0 +1,123 @@
+/*
+ * Copyright (c) 2016 Cadence Design Systems, Inc.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef XTENSA_SYS_IO_H
+#define XTENSA_SYS_IO_H
+
+#if !defined(_ASMLANGUAGE)
+
+#include <sys_io.h>
+
+/* Memory mapped registers I/O functions */
+
+static ALWAYS_INLINE uint32_t sys_read32(mem_addr_t addr)
+{
+	return *(volatile uint32_t *)addr;
+}
+
+
+static ALWAYS_INLINE void sys_write32(uint32_t data, mem_addr_t addr)
+{
+	*(volatile uint32_t *)addr = data;
+}
+
+
+/* Memory bit manipulation functions */
+
+static ALWAYS_INLINE void sys_set_bit(mem_addr_t addr, unsigned int bit)
+{
+	uint32_t temp = *(volatile uint32_t *)addr;
+
+	*(volatile uint32_t *)addr = temp | (1 << bit);
+}
+
+static ALWAYS_INLINE void sys_clear_bit(mem_addr_t addr, unsigned int bit)
+{
+	uint32_t temp = *(volatile uint32_t *)addr;
+
+	*(volatile uint32_t *)addr = temp & ~(1 << bit);
+}
+
+static ALWAYS_INLINE int sys_test_bit(mem_addr_t addr, unsigned int bit)
+{
+	int temp = *(volatile int *)addr;
+	return (int)(temp & (1 << bit));
+}
+
+static ALWAYS_INLINE int sys_test_and_set_bit(mem_addr_t addr, unsigned int bit)
+{
+	int retval = (*(volatile int *)addr) & (1 << bit);
+	*(volatile int *)addr = (*(volatile int *)addr) | (1 << bit);
+	return retval;
+}
+
+static ALWAYS_INLINE int sys_test_and_clear_bit(mem_addr_t addr, unsigned int bit)
+{
+	int retval = (*(volatile int *)addr) & (1 << bit);
+	*(volatile int *)addr = (*(volatile int *)addr) & ~(1 << bit);
+	return retval;
+}
+
+static ALWAYS_INLINE
+	void sys_bitfield_set_bit(mem_addr_t addr, unsigned int bit)
+{
+	/* Doing memory offsets in terms of 32-bit values to prevent
+	 * alignment issues
+	 */
+	sys_set_bit(addr + ((bit >> 5) << 2), bit & 0x1F);
+}
+
+static ALWAYS_INLINE
+	void sys_bitfield_clear_bit(mem_addr_t addr, unsigned int bit)
+{
+	sys_clear_bit(addr + ((bit >> 5) << 2), bit & 0x1F);
+}
+
+static ALWAYS_INLINE
+	int sys_bitfield_test_bit(mem_addr_t addr, unsigned int bit)
+{
+	return sys_test_bit(addr + ((bit >> 5) << 2), bit & 0x1F);
+}
+
+
+static ALWAYS_INLINE
+	int sys_bitfield_test_and_set_bit(mem_addr_t addr, unsigned int bit)
+{
+	int ret;
+
+	ret = sys_bitfield_test_bit(addr, bit);
+	sys_bitfield_set_bit(addr, bit);
+
+	return ret;
+}
+
+static ALWAYS_INLINE
+	int sys_bitfield_test_and_clear_bit(mem_addr_t addr, unsigned int bit)
+{
+	int ret;
+
+	ret = sys_bitfield_test_bit(addr, bit);
+	sys_bitfield_clear_bit(addr, bit);
+
+	return ret;
+}
+
+
+#endif /* !_ASMLANGUAGE */
+
+
+#endif /* XTENSA_SYS_IO_H */