drivers: pwm: add driver for the RV32M1 Timer/PWM module
Add driver for the OpenISA Timer/PWM (TPM) module present in the RV32M1 SoC. Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
This commit is contained in:
Henrik Brix Andersen
Maureen Helm
parent
f3144644bd
commit
3e7ca8f2ad
4 changed files with 228 additions and 0 deletions
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@ -15,6 +15,7 @@ zephyr_library_sources_ifdef(CONFIG_PWM_SAM pwm_sam.c)
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zephyr_library_sources_ifdef(CONFIG_PWM_MCUX pwm_mcux.c)
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zephyr_library_sources_ifdef(CONFIG_PWM_XEC pwm_mchp_xec.c)
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zephyr_library_sources_ifdef(CONFIG_PWM_LITEX pwm_litex.c)
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zephyr_library_sources_ifdef(CONFIG_PWM_RV32M1_TPM pwm_rv32m1_tpm.c)
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zephyr_library_sources_ifdef(CONFIG_USERSPACE pwm_handlers.c)
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zephyr_library_sources_ifdef(CONFIG_PWM_SHELL pwm_shell.c)
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@ -61,4 +61,6 @@ source "drivers/pwm/Kconfig.xec"
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source "drivers/pwm/Kconfig.litex"
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source "drivers/pwm/Kconfig.rv32m1_tpm"
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endif # PWM
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10
drivers/pwm/Kconfig.rv32m1_tpm
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10
drivers/pwm/Kconfig.rv32m1_tpm
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@ -0,0 +1,10 @@
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# RV32M1 TPM PWM
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# Copyright (c) 2019 Henrik Brix Andersen <henrik@brixandersen.dk>
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# SPDX-License-Identifier: Apache-2.0
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config PWM_RV32M1_TPM
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bool "RV32M1 TPM PWM driver"
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depends on HAS_RV32M1_TPM && CLOCK_CONTROL
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help
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Enable the RV32M1 TPM PWM driver.
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215
drivers/pwm/pwm_rv32m1_tpm.c
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215
drivers/pwm/pwm_rv32m1_tpm.c
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@ -0,0 +1,215 @@
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/*
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* Copyright 2019 Henrik Brix Andersen <henrik@brixandersen.dk>
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*
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* Heavily based on pwm_mcux_ftm.c, which is:
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* Copyright (c) 2017, NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <drivers/clock_control.h>
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#include <errno.h>
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#include <drivers/pwm.h>
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#include <soc.h>
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#include <fsl_tpm.h>
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#include <fsl_clock.h>
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#define LOG_LEVEL CONFIG_PWM_LOG_LEVEL
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#include <logging/log.h>
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LOG_MODULE_REGISTER(pwm_rv32m1_tpm);
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#define MAX_CHANNELS ARRAY_SIZE(TPM0->CONTROLS)
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struct rv32m1_tpm_config {
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TPM_Type *base;
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char *clock_name;
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clock_control_subsys_t clock_subsys;
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tpm_clock_source_t tpm_clock_source;
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tpm_clock_prescale_t prescale;
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u8_t channel_count;
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tpm_pwm_mode_t mode;
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};
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struct rv32m1_tpm_data {
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u32_t clock_freq;
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u32_t period_cycles;
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tpm_chnl_pwm_signal_param_t channel[MAX_CHANNELS];
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};
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static int rv32m1_tpm_pin_set(struct device *dev, u32_t pwm,
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u32_t period_cycles, u32_t pulse_cycles,
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pwm_flags_t flags)
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{
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const struct rv32m1_tpm_config *config = dev->config->config_info;
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struct rv32m1_tpm_data *data = dev->driver_data;
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u8_t duty_cycle;
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if ((period_cycles == 0U) || (pulse_cycles > period_cycles)) {
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LOG_ERR("Invalid combination: period_cycles=%d, "
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"pulse_cycles=%d", period_cycles, pulse_cycles);
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return -EINVAL;
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}
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if (pwm >= config->channel_count) {
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LOG_ERR("Invalid channel");
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return -ENOTSUP;
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}
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duty_cycle = pulse_cycles * 100U / period_cycles;
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data->channel[pwm].dutyCyclePercent = duty_cycle;
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if ((flags & PWM_POLARITY_INVERTED) == 0) {
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data->channel[pwm].level = kTPM_HighTrue;
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} else {
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data->channel[pwm].level = kTPM_LowTrue;
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}
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LOG_DBG("pulse_cycles=%d, period_cycles=%d, duty_cycle=%d, flags=%d",
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pulse_cycles, period_cycles, duty_cycle, flags);
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if (period_cycles != data->period_cycles) {
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u32_t pwm_freq;
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status_t status;
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if (data->period_cycles != 0) {
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/* Only warn when not changing from zero */
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LOG_WRN("Changing period cycles from %d to %d"
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" affects all %d channels in %s",
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data->period_cycles, period_cycles,
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config->channel_count, dev->config->name);
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}
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data->period_cycles = period_cycles;
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pwm_freq = (data->clock_freq >> config->prescale) /
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period_cycles;
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LOG_DBG("pwm_freq=%d, clock_freq=%d", pwm_freq,
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data->clock_freq);
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if (pwm_freq == 0U) {
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LOG_ERR("Could not set up pwm_freq=%d", pwm_freq);
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return -EINVAL;
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}
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TPM_StopTimer(config->base);
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status = TPM_SetupPwm(config->base, data->channel,
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config->channel_count, config->mode,
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pwm_freq, data->clock_freq);
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if (status != kStatus_Success) {
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LOG_ERR("Could not set up pwm");
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return -ENOTSUP;
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}
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TPM_StartTimer(config->base, config->tpm_clock_source);
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} else {
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TPM_UpdateChnlEdgeLevelSelect(config->base, pwm,
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data->channel[pwm].level);
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TPM_UpdatePwmDutycycle(config->base, pwm, config->mode,
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duty_cycle);
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}
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return 0;
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}
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static int rv32m1_tpm_get_cycles_per_sec(struct device *dev, u32_t pwm,
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u64_t *cycles)
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{
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const struct rv32m1_tpm_config *config = dev->config->config_info;
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struct rv32m1_tpm_data *data = dev->driver_data;
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*cycles = data->clock_freq >> config->prescale;
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return 0;
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}
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static int rv32m1_tpm_init(struct device *dev)
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{
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const struct rv32m1_tpm_config *config = dev->config->config_info;
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struct rv32m1_tpm_data *data = dev->driver_data;
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tpm_chnl_pwm_signal_param_t *channel = data->channel;
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struct device *clock_dev;
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tpm_config_t tpm_config;
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int i;
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if (config->channel_count > ARRAY_SIZE(data->channel)) {
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LOG_ERR("Invalid channel count");
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return -EINVAL;
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}
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clock_dev = device_get_binding(config->clock_name);
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if (clock_dev == NULL) {
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LOG_ERR("Could not get clock device");
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return -EINVAL;
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}
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if (clock_control_on(clock_dev, config->clock_subsys)) {
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LOG_ERR("Could not turn on clock");
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return -EINVAL;
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}
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if (clock_control_get_rate(clock_dev, config->clock_subsys,
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&data->clock_freq)) {
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LOG_ERR("Could not get clock frequency");
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return -EINVAL;
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}
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for (i = 0; i < config->channel_count; i++) {
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channel->chnlNumber = i;
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channel->level = kTPM_NoPwmSignal;
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channel->dutyCyclePercent = 0;
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channel->firstEdgeDelayPercent = 0;
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channel++;
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}
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TPM_GetDefaultConfig(&tpm_config);
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tpm_config.prescale = config->prescale;
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TPM_Init(config->base, &tpm_config);
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return 0;
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}
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static const struct pwm_driver_api rv32m1_tpm_driver_api = {
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.pin_set = rv32m1_tpm_pin_set,
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.get_cycles_per_sec = rv32m1_tpm_get_cycles_per_sec,
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};
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#define TPM_DEVICE(n) \
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static const struct rv32m1_tpm_config rv32m1_tpm_config_##n = { \
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.base = (TPM_Type *) \
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DT_INST_##n##_OPENISA_RV32M1_TPM_BASE_ADDRESS, \
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.clock_name = \
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DT_INST_##n##_OPENISA_RV32M1_TPM_CLOCK_CONTROLLER, \
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.clock_subsys = (clock_control_subsys_t) \
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DT_INST_##n##_OPENISA_RV32M1_TPM_CLOCK_NAME, \
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.tpm_clock_source = kTPM_SystemClock, \
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.prescale = kTPM_Prescale_Divide_16, \
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.channel_count = FSL_FEATURE_TPM_CHANNEL_COUNTn((TPM_Type *) \
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DT_INST_##n##_OPENISA_RV32M1_TPM_BASE_ADDRESS), \
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.mode = kTPM_EdgeAlignedPwm, \
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}; \
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static struct rv32m1_tpm_data rv32m1_tpm_data_##n; \
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DEVICE_AND_API_INIT(rv32m1_tpm_##n, \
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DT_INST_##n##_OPENISA_RV32M1_TPM_LABEL, \
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&rv32m1_tpm_init, &rv32m1_tpm_data_##n, \
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&rv32m1_tpm_config_##n, \
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POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, \
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&rv32m1_tpm_driver_api)
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#if DT_INST_0_OPENISA_RV32M1_TPM
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TPM_DEVICE(0);
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#endif /* DT_INST_0_OPENISA_RV32M1_TPM */
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#if DT_INST_1_OPENISA_RV32M1_TPM
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TPM_DEVICE(1);
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#endif /* DT_INST_1_OPENISA_RV32M1_TPM */
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#if DT_INST_2_OPENISA_RV32M1_TPM
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TPM_DEVICE(2);
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#endif /* DT_INST_2_OPENISA_RV32M1_TPM */
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#if DT_INST_3_OPENISA_RV32M1_TPM
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TPM_DEVICE(3);
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#endif /* DT_INST_3_OPENISA_RV32M1_TPM */
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