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arm: Fix assembler layout.

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Adjust the layout of various ARM assember files to conform to the norm
used in the majority of files.

Change-Id: Ia5007628be5ad36ef587946861c6ea90a8062585
Signed-off-by: Marcus Shawcroft <marcus.shawcroft@arm.com>
This commit is contained in:
Marcus Shawcroft 2016-12-31 13:03:53 +00:00 • committed by Kumar Gala
commit 3de84ae88e
3 changed files with 69 additions and 65 deletions
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80
arch/arm/core/cpu_idle.S
View file

@ -57,10 +57,10 @@ GTEXT(k_cpu_atomic_idle)
*/ */
SECTION_FUNC(TEXT, _CpuIdleInit) SECTION_FUNC(TEXT, _CpuIdleInit)
ldr r1, =_SCB_SCR ldr r1, =_SCB_SCR
movs.n r2, #_SCR_INIT_BITS movs.n r2, #_SCR_INIT_BITS
str r2, [r1] str r2, [r1]
bx lr bx lr
#ifdef CONFIG_SYS_POWER_MANAGEMENT #ifdef CONFIG_SYS_POWER_MANAGEMENT
@ -78,9 +78,9 @@ SECTION_FUNC(TEXT, _CpuIdleInit)
*/ */
SECTION_FUNC(TEXT, _NanoIdleValGet) SECTION_FUNC(TEXT, _NanoIdleValGet)
ldr r0, =_kernel ldr r0, =_kernel
ldr r0, [r0, #_kernel_offset_to_idle] ldr r0, [r0, #_kernel_offset_to_idle]
bx lr bx lr
/** /**
* *
@ -96,10 +96,10 @@ SECTION_FUNC(TEXT, _NanoIdleValGet)
*/ */
SECTION_FUNC(TEXT, _NanoIdleValClear) SECTION_FUNC(TEXT, _NanoIdleValClear)
ldr r0, =_kernel ldr r0, =_kernel
eors.n r1, r1 eors.n r1, r1
str r1, [r0, #_kernel_offset_to_idle] str r1, [r0, #_kernel_offset_to_idle]
bx lr bx lr
#endif /* CONFIG_SYS_POWER_MANAGEMENT */ #endif /* CONFIG_SYS_POWER_MANAGEMENT */
@ -128,16 +128,16 @@ SECTION_FUNC(TEXT, k_cpu_idle)
#endif #endif
#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS) #if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
cpsie i cpsie i
#else /* CONFIG_CPU_CORTEX_M3_M4 */ #else /* CONFIG_CPU_CORTEX_M3_M4 */
/* clear BASEPRI so wfi is awakened by incoming interrupts */ /* clear BASEPRI so wfi is awakened by incoming interrupts */
eors.n r0, r0 eors.n r0, r0
msr BASEPRI, r0 msr BASEPRI, r0
#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */ #endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */
wfi wfi
bx lr bx lr
/** /**
* *
@ -169,38 +169,38 @@ SECTION_FUNC(TEXT, k_cpu_atomic_idle)
mov lr, r1 mov lr, r1
#endif #endif
/* /*
* Lock PRIMASK while sleeping: wfe will still get interrupted by incoming * Lock PRIMASK while sleeping: wfe will still get interrupted by
* interrupts but the CPU will not service them right away. * incoming interrupts but the CPU will not service them right away.
*/ */
cpsid i cpsid i
/* /*
* No need to set SEVONPEND, it's set once in _CpuIdleInit() and never * No need to set SEVONPEND, it's set once in _CpuIdleInit() and never
* touched again. * touched again.
*/ */
/* r0: interrupt mask from caller */ /* r0: interrupt mask from caller */
#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS) #if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
/* No BASEPRI, call wfe directly (SEVONPEND set in _CpuIdleInit()) */ /* No BASEPRI, call wfe directly (SEVONPEND set in _CpuIdleInit()) */
wfe wfe
cmp r0, #0 cmp r0, #0
bne _irq_disabled bne _irq_disabled
cpsie i cpsie i
_irq_disabled: _irq_disabled:
#else /* CONFIG_CPU_CORTEX_M3_M4 */ #else /* CONFIG_CPU_CORTEX_M3_M4 */
/* r1: zero, for setting BASEPRI (needs a register) */ /* r1: zero, for setting BASEPRI (needs a register) */
eors.n r1, r1 eors.n r1, r1
/* unlock BASEPRI so wfe gets interrupted by incoming interrupts */ /* unlock BASEPRI so wfe gets interrupted by incoming interrupts */
msr BASEPRI, r1 msr BASEPRI, r1
wfe wfe
msr BASEPRI, r0 msr BASEPRI, r0
cpsie i cpsie i
#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */ #endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */
bx lr bx lr

52
arch/arm/core/fault_s.S
View file

@ -73,40 +73,44 @@ SECTION_SUBSEC_FUNC(TEXT,__fault,__debug_monitor)
SECTION_SUBSEC_FUNC(TEXT,__fault,__reserved) SECTION_SUBSEC_FUNC(TEXT,__fault,__reserved)
#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS) #if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
/* force unlock interrupts */ /* force unlock interrupts */
cpsie i cpsie i
/* Use EXC_RETURN state to find out if stack frame is on the MSP or PSP */ /* Use EXC_RETURN state to find out if stack frame is on the
ldr r0, =0x4 * MSP or PSP
mov r1, lr */
tst r1, r0 ldr r0, =0x4
beq _stack_frame_msp mov r1, lr
mrs r0, PSP tst r1, r0
bne _stack_frame_endif beq _stack_frame_msp
mrs r0, PSP
bne _stack_frame_endif
_stack_frame_msp: _stack_frame_msp:
mrs r0, MSP mrs r0, MSP
_stack_frame_endif: _stack_frame_endif:
#else /* CONFIG_CPU_CORTEX_M3_M4 */ #else /* CONFIG_CPU_CORTEX_M3_M4 */
/* force unlock interrupts */ /* force unlock interrupts */
eors.n r0, r0 eors.n r0, r0
msr BASEPRI, r0 msr BASEPRI, r0
/* this reimplements _ScbIsNestedExc() */ /* this reimplements _ScbIsNestedExc() */
ldr ip, =_SCS_ICSR ldr ip, =_SCS_ICSR
ldr ip, [ip] ldr ip, [ip]
ands.w ip, #_SCS_ICSR_RETTOBASE ands.w ip, #_SCS_ICSR_RETTOBASE
ite eq /* is the RETTOBASE bit zero ? */ ite eq /* is the RETTOBASE bit zero ? */
mrseq r0, MSP /* if so, we're not returning to thread mode, thus this mrseq r0, MSP /* if so, we're not returning to thread mode,
* is a nested exception: the stack frame is on the MSP */ * thus this is a nested exception: the stack
mrsne r0, PSP /* if not, we are returning to thread mode, thus this is * frame is on the MSP */
* not a nested exception: the stack frame is on the PSP */ mrsne r0, PSP /* if not, we are returning to thread mode, thus
* this is not a nested exception: the stack
* frame is on the PSP */
#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */ #endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */
push {lr} push {lr}
bl _Fault bl _Fault
pop {pc} pop {pc}
.end .end

2
arch/arm/core/isr_wrapper.S
View file

@ -110,7 +110,7 @@ _idle_state_cleared:
#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */ #endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */
ldr r1, =_sw_isr_table ldr r1, =_sw_isr_table
add r1, r1, r0 /* table entry: ISRs must have their MSB set to stay add r1, r1, r0 /* table entry: ISRs must have their MSB set to stay
* in thumb mode */ * in thumb mode */
ldm r1!,{r0,r3} /* arg in r0, ISR in r3 */ ldm r1!,{r0,r3} /* arg in r0, ISR in r3 */
blx r3 /* call ISR */ blx r3 /* call ISR */