arm: Fix assembler layout.
Adjust the layout of various ARM assember files to conform to the norm used in the majority of files. Change-Id: Ia5007628be5ad36ef587946861c6ea90a8062585 Signed-off-by: Marcus Shawcroft <marcus.shawcroft@arm.com>
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acca033468
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3 changed files with 69 additions and 65 deletions
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@ -57,10 +57,10 @@ GTEXT(k_cpu_atomic_idle)
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*/
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SECTION_FUNC(TEXT, _CpuIdleInit)
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ldr r1, =_SCB_SCR
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movs.n r2, #_SCR_INIT_BITS
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str r2, [r1]
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bx lr
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ldr r1, =_SCB_SCR
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movs.n r2, #_SCR_INIT_BITS
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str r2, [r1]
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bx lr
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#ifdef CONFIG_SYS_POWER_MANAGEMENT
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@ -78,9 +78,9 @@ SECTION_FUNC(TEXT, _CpuIdleInit)
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*/
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SECTION_FUNC(TEXT, _NanoIdleValGet)
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ldr r0, =_kernel
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ldr r0, [r0, #_kernel_offset_to_idle]
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bx lr
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ldr r0, =_kernel
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ldr r0, [r0, #_kernel_offset_to_idle]
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bx lr
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/**
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*
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@ -96,10 +96,10 @@ SECTION_FUNC(TEXT, _NanoIdleValGet)
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*/
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SECTION_FUNC(TEXT, _NanoIdleValClear)
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ldr r0, =_kernel
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eors.n r1, r1
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str r1, [r0, #_kernel_offset_to_idle]
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bx lr
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ldr r0, =_kernel
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eors.n r1, r1
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str r1, [r0, #_kernel_offset_to_idle]
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bx lr
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#endif /* CONFIG_SYS_POWER_MANAGEMENT */
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@ -128,16 +128,16 @@ SECTION_FUNC(TEXT, k_cpu_idle)
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#endif
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#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
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cpsie i
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cpsie i
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#else /* CONFIG_CPU_CORTEX_M3_M4 */
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/* clear BASEPRI so wfi is awakened by incoming interrupts */
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eors.n r0, r0
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msr BASEPRI, r0
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/* clear BASEPRI so wfi is awakened by incoming interrupts */
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eors.n r0, r0
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msr BASEPRI, r0
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#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */
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wfi
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wfi
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bx lr
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bx lr
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/**
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*
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@ -169,38 +169,38 @@ SECTION_FUNC(TEXT, k_cpu_atomic_idle)
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mov lr, r1
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#endif
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/*
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* Lock PRIMASK while sleeping: wfe will still get interrupted by incoming
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* interrupts but the CPU will not service them right away.
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*/
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cpsid i
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/*
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* Lock PRIMASK while sleeping: wfe will still get interrupted by
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* incoming interrupts but the CPU will not service them right away.
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*/
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cpsid i
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/*
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* No need to set SEVONPEND, it's set once in _CpuIdleInit() and never
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* touched again.
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*/
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/*
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* No need to set SEVONPEND, it's set once in _CpuIdleInit() and never
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* touched again.
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*/
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/* r0: interrupt mask from caller */
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/* r0: interrupt mask from caller */
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#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
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/* No BASEPRI, call wfe directly (SEVONPEND set in _CpuIdleInit()) */
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wfe
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/* No BASEPRI, call wfe directly (SEVONPEND set in _CpuIdleInit()) */
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wfe
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cmp r0, #0
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bne _irq_disabled
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cpsie i
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cmp r0, #0
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bne _irq_disabled
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cpsie i
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_irq_disabled:
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#else /* CONFIG_CPU_CORTEX_M3_M4 */
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/* r1: zero, for setting BASEPRI (needs a register) */
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eors.n r1, r1
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/* r1: zero, for setting BASEPRI (needs a register) */
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eors.n r1, r1
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/* unlock BASEPRI so wfe gets interrupted by incoming interrupts */
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msr BASEPRI, r1
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/* unlock BASEPRI so wfe gets interrupted by incoming interrupts */
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msr BASEPRI, r1
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wfe
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wfe
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msr BASEPRI, r0
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cpsie i
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msr BASEPRI, r0
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cpsie i
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#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */
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bx lr
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bx lr
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@ -73,40 +73,44 @@ SECTION_SUBSEC_FUNC(TEXT,__fault,__debug_monitor)
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SECTION_SUBSEC_FUNC(TEXT,__fault,__reserved)
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#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
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/* force unlock interrupts */
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cpsie i
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/* force unlock interrupts */
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cpsie i
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/* Use EXC_RETURN state to find out if stack frame is on the MSP or PSP */
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ldr r0, =0x4
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mov r1, lr
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tst r1, r0
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beq _stack_frame_msp
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mrs r0, PSP
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bne _stack_frame_endif
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/* Use EXC_RETURN state to find out if stack frame is on the
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* MSP or PSP
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*/
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ldr r0, =0x4
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mov r1, lr
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tst r1, r0
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beq _stack_frame_msp
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mrs r0, PSP
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bne _stack_frame_endif
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_stack_frame_msp:
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mrs r0, MSP
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mrs r0, MSP
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_stack_frame_endif:
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#else /* CONFIG_CPU_CORTEX_M3_M4 */
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/* force unlock interrupts */
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eors.n r0, r0
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msr BASEPRI, r0
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/* force unlock interrupts */
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eors.n r0, r0
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msr BASEPRI, r0
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/* this reimplements _ScbIsNestedExc() */
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ldr ip, =_SCS_ICSR
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ldr ip, [ip]
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ands.w ip, #_SCS_ICSR_RETTOBASE
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ldr ip, =_SCS_ICSR
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ldr ip, [ip]
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ands.w ip, #_SCS_ICSR_RETTOBASE
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ite eq /* is the RETTOBASE bit zero ? */
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mrseq r0, MSP /* if so, we're not returning to thread mode, thus this
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* is a nested exception: the stack frame is on the MSP */
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mrsne r0, PSP /* if not, we are returning to thread mode, thus this is
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* not a nested exception: the stack frame is on the PSP */
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mrseq r0, MSP /* if so, we're not returning to thread mode,
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* thus this is a nested exception: the stack
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* frame is on the MSP */
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mrsne r0, PSP /* if not, we are returning to thread mode, thus
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* this is not a nested exception: the stack
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* frame is on the PSP */
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#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */
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push {lr}
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bl _Fault
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push {lr}
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bl _Fault
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pop {pc}
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pop {pc}
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.end
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.end
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@ -110,7 +110,7 @@ _idle_state_cleared:
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#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */
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ldr r1, =_sw_isr_table
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add r1, r1, r0 /* table entry: ISRs must have their MSB set to stay
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* in thumb mode */
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* in thumb mode */
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ldm r1!,{r0,r3} /* arg in r0, ISR in r3 */
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blx r3 /* call ISR */
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