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rimage: update rimage: add configuration and extended manifest

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rimage dropped its "-m" parameter and switched over to using "-c"
for a configuration file, including a target name.

Add support for extended manifest for all cAVS versions.

Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
This commit is contained in:
Guennadi Liakhovetski 2020-10-27 12:48:36 +01:00 • committed by Anas Nashif
commit 3de40b48c3
9 changed files with 83 additions and 2 deletions
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2
soc/xtensa/intel_adsp/cavs_v15/include/soc/memory.h
View file

@ -142,6 +142,8 @@
#define LOG_ENTRY_ELF_BASE 0x20000000
#define LOG_ENTRY_ELF_SIZE 0x2000000
#define EXT_MANIFEST_ELF_BASE (LOG_ENTRY_ELF_BASE + LOG_ENTRY_ELF_SIZE)
#define EXT_MANIFEST_ELF_SIZE 0x2000000
#define SRAM_ALIAS_BASE 0x9E000000
#define SRAM_ALIAS_MASK 0xFF000000

15
soc/xtensa/intel_adsp/cavs_v15/linker.ld
View file

@ -132,6 +132,9 @@ MEMORY
static_log_entries_seg (!ari) :
org = LOG_ENTRY_ELF_BASE,
len = LOG_ENTRY_ELF_SIZE
fw_metadata_seg (!ari) :
org = EXT_MANIFEST_ELF_BASE,
len = EXT_MANIFEST_ELF_SIZE
}
PHDRS
@ -161,6 +164,7 @@ PHDRS
ucram_phdr PT_LOAD;
static_uuid_entries_phdr PT_NOTE;
static_log_entries_phdr PT_NOTE;
metadata_entries_phdr PT_NOTE;
}
_rom_store_table = 0;
PROVIDE(_memmap_vecbase_reset = XCHAL_VECBASE_RESET_PADDR_SRAM);
@ -205,6 +209,11 @@ _memmap_cacheattr_bp_allvalid = 0x22222222;
_memmap_cacheattr_intel_cavs15_adsp = 0xFF42FFF2;
PROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_intel_cavs15_adsp);
_EXT_MAN_ALIGN_ = 16;
EXTERN(ext_man_fw_ver)
EXTERN(ext_man_cavs_config)
SECTIONS
{
@ -567,4 +576,10 @@ SECTIONS
{
*(*.static_log*)
} > static_log_entries_seg :static_log_entries_phdr
.fw_metadata (COPY) : ALIGN(1024)
{
KEEP (*(.fw_metadata))
. = ALIGN(_EXT_MAN_ALIGN_);
} >fw_metadata_seg :metadata_entries_phdr
}

2
soc/xtensa/intel_adsp/cavs_v18/include/soc/memory.h
View file

@ -139,6 +139,8 @@
#define LOG_ENTRY_ELF_BASE 0x20000000
#define LOG_ENTRY_ELF_SIZE 0x2000000
#define EXT_MANIFEST_ELF_BASE (LOG_ENTRY_ELF_BASE + LOG_ENTRY_ELF_SIZE)
#define EXT_MANIFEST_ELF_SIZE 0x2000000
#define SRAM_ALIAS_BASE 0x9E000000
#define SRAM_ALIAS_MASK 0xFF000000

15
soc/xtensa/intel_adsp/cavs_v18/linker.ld
View file

@ -112,6 +112,9 @@ MEMORY
static_log_entries_seg (!ari) :
org = LOG_ENTRY_ELF_BASE,
len = LOG_ENTRY_ELF_SIZE
fw_metadata_seg (!ari) :
org = EXT_MANIFEST_ELF_BASE,
len = EXT_MANIFEST_ELF_SIZE
}
PHDRS
@ -141,6 +144,7 @@ PHDRS
static_uuid_entries_phdr PT_NOTE;
static_log_entries_phdr PT_NOTE;
metadata_entries_phdr PT_NOTE;
}
_rom_store_table = 0;
PROVIDE(_memmap_vecbase_reset = XCHAL_VECBASE_RESET_PADDR_SRAM);
@ -194,6 +198,11 @@ _memmap_cacheattr_intel_cavs18_adsp = 0xFF22FFF2;
#endif
PROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_intel_cavs18_adsp);
_EXT_MAN_ALIGN_ = 16;
EXTERN(ext_man_fw_ver)
EXTERN(ext_man_cavs_config)
SECTIONS
{
@ -532,4 +541,10 @@ SECTIONS
{
*(*.static_log*)
} > static_log_entries_seg :static_log_entries_phdr
.fw_metadata (COPY) : ALIGN(1024)
{
KEEP (*(.fw_metadata))
. = ALIGN(_EXT_MAN_ALIGN_);
} >fw_metadata_seg :metadata_entries_phdr
}

2
soc/xtensa/intel_adsp/cavs_v20/include/soc/memory.h
View file

@ -139,6 +139,8 @@
#define LOG_ENTRY_ELF_BASE 0x20000000
#define LOG_ENTRY_ELF_SIZE 0x2000000
#define EXT_MANIFEST_ELF_BASE (LOG_ENTRY_ELF_BASE + LOG_ENTRY_ELF_SIZE)
#define EXT_MANIFEST_ELF_SIZE 0x2000000
#define SRAM_ALIAS_BASE 0x9E000000
#define SRAM_ALIAS_MASK 0xFF000000

14
soc/xtensa/intel_adsp/cavs_v20/linker.ld
View file

@ -112,8 +112,15 @@ MEMORY
static_log_entries_seg (!ari) :
org = LOG_ENTRY_ELF_BASE,
len = LOG_ENTRY_ELF_SIZE
fw_metadata_seg (!ari) :
org = EXT_MANIFEST_ELF_BASE,
len = EXT_MANIFEST_ELF_SIZE
}
_EXT_MAN_ALIGN_ = 16;
EXTERN(ext_man_fw_ver)
EXTERN(ext_man_cavs_config)
PHDRS
{
vector_memory_lit_phdr PT_LOAD;
@ -141,6 +148,7 @@ PHDRS
static_uuid_entries_phdr PT_NOTE;
static_log_entries_phdr PT_NOTE;
metadata_entries_phdr PT_NOTE;
}
_rom_store_table = 0;
PROVIDE(_memmap_vecbase_reset = XCHAL_VECBASE_RESET_PADDR_SRAM);
@ -532,4 +540,10 @@ SECTIONS
{
*(*.static_log*)
} > static_log_entries_seg :static_log_entries_phdr
.fw_metadata (COPY) : ALIGN(1024)
{
KEEP (*(.fw_metadata))
. = ALIGN(_EXT_MAN_ALIGN_);
} >fw_metadata_seg :metadata_entries_phdr
}

2
soc/xtensa/intel_adsp/cavs_v25/include/soc/memory.h
View file

@ -139,6 +139,8 @@
#define LOG_ENTRY_ELF_BASE 0x20000000
#define LOG_ENTRY_ELF_SIZE 0x2000000
#define EXT_MANIFEST_ELF_BASE (LOG_ENTRY_ELF_BASE + LOG_ENTRY_ELF_SIZE)
#define EXT_MANIFEST_ELF_SIZE 0x2000000
#define SRAM_ALIAS_BASE 0x9E000000
#define SRAM_ALIAS_MASK 0xFF000000

15
soc/xtensa/intel_adsp/cavs_v25/linker.ld
View file

@ -112,6 +112,9 @@ MEMORY
static_log_entries_seg (!ari) :
org = LOG_ENTRY_ELF_BASE,
len = LOG_ENTRY_ELF_SIZE
fw_metadata_seg (!ari) :
org = EXT_MANIFEST_ELF_BASE,
len = EXT_MANIFEST_ELF_SIZE
lpsram_alt_reset_vec_seg :
org = LP_SRAM_ALT_RESET_VEC_BASE,
@ -154,6 +157,7 @@ PHDRS
static_uuid_entries_phdr PT_NOTE;
static_log_entries_phdr PT_NOTE;
metadata_entries_phdr PT_NOTE;
lpsram_mem_phdr PT_LOAD;
sram_alt_fw_reset_vec_phdr PT_LOAD;
@ -214,6 +218,11 @@ _memmap_cacheattr_intel_cavs25_adsp = 0xFF22FFF2;
#endif
PROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_intel_cavs25_adsp);
_EXT_MAN_ALIGN_ = 16;
EXTERN(ext_man_fw_ver)
EXTERN(ext_man_cavs_config)
SECTIONS
{
@ -600,4 +609,10 @@ SECTIONS
{
*(*.static_log*)
} > static_log_entries_seg :static_log_entries_phdr
.fw_metadata (COPY) : ALIGN(1024)
{
KEEP (*(.fw_metadata))
. = ALIGN(_EXT_MAN_ALIGN_);
} >fw_metadata_seg :metadata_entries_phdr
}