arch: arm64: fix the wrong way to send ipi interrupt

On GICv3, when we send an IPI interrupt, aff3, aff2 and aff1 should
be assigned a value corespond to a PE for which interrupt will be
generated. target_list only corresponds to aff0.

On real hardware, aff3, aff2, aff1 and aff0 should be treated as a
whole to determine a PE.

Signed-off-by: Huifeng Zhang <Huifeng.Zhang@arm.com>
This commit is contained in:
Huifeng Zhang 2022-07-05 14:13:23 +08:00 committed by Fabio Baltieri
commit 3d81d7f23f
3 changed files with 20 additions and 14 deletions

View file

@ -89,7 +89,10 @@ static inline void trigger_irq(int irq)
sys_write32(GICD_SGIR_TGTFILT_REQONLY | GICD_SGIR_SGIINTID(irq),
GICD_SGIR);
#else
gic_raise_sgi(irq, GET_MPIDR(), BIT(MPIDR_TO_CORE(GET_MPIDR())));
uint64_t mpidr = GET_MPIDR();
uint8_t aff0 = MPIDR_AFFLVL(mpidr, 0);
gic_raise_sgi(irq, mpidr, BIT(aff0));
#endif
}