arch: arm64: fix the wrong way to send ipi interrupt
On GICv3, when we send an IPI interrupt, aff3, aff2 and aff1 should be assigned a value corespond to a PE for which interrupt will be generated. target_list only corresponds to aff0. On real hardware, aff3, aff2, aff1 and aff0 should be treated as a whole to determine a PE. Signed-off-by: Huifeng Zhang <Huifeng.Zhang@arm.com>
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3 changed files with 20 additions and 14 deletions
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@ -89,7 +89,10 @@ static inline void trigger_irq(int irq)
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sys_write32(GICD_SGIR_TGTFILT_REQONLY | GICD_SGIR_SGIINTID(irq),
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GICD_SGIR);
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#else
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gic_raise_sgi(irq, GET_MPIDR(), BIT(MPIDR_TO_CORE(GET_MPIDR())));
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uint64_t mpidr = GET_MPIDR();
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uint8_t aff0 = MPIDR_AFFLVL(mpidr, 0);
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gic_raise_sgi(irq, mpidr, BIT(aff0));
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#endif
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}
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