diff --git a/dts/arm/Makefile b/dts/arm/Makefile
index fb604da20d9..3659a83811c 100644
--- a/dts/arm/Makefile
+++ b/dts/arm/Makefile
@@ -1,5 +1,6 @@
 ifeq ($(CONFIG_HAS_DTS),y)
 dtb-$(CONFIG_BOARD_FRDM_K64F)	=	frdm_k64f.dts_compiled
 dtb-$(CONFIG_BOARD_HEXIWEAR_K64)	=	hexiwear_k64.dts_compiled
+dtb-$(CONFIG_BOARD_CC3200_LAUNCHXL)	=	cc3200_launchxl.dts_compiled
 always	:= $(dtb-y)
 endif
diff --git a/dts/arm/cc3200_launchxl.dts b/dts/arm/cc3200_launchxl.dts
new file mode 100644
index 00000000000..2b9df631b70
--- /dev/null
+++ b/dts/arm/cc3200_launchxl.dts
@@ -0,0 +1,22 @@
+/dts-v1/;
+
+#include "cc32xx_launchxl.dtsi"
+
+/ {
+	model = "TI CC3200 LaunchXL";
+	compatible = "ti,cc32xx";
+
+	aliases {
+		uart_0 = &uart0;
+		uart_1 = &uart1;
+	};
+
+	chosen {
+		zephyr,sram = &sram0;
+		zephyr,flash = &flash0;
+	};
+};
+
+&uart0 {
+	status = "ok";
+};
diff --git a/dts/arm/cc3200_launchxl.fixup b/dts/arm/cc3200_launchxl.fixup
new file mode 100644
index 00000000000..a28d91f9d72
--- /dev/null
+++ b/dts/arm/cc3200_launchxl.fixup
@@ -0,0 +1,7 @@
+#define CONFIG_NUM_IRQS			ARM_ARMV7M_NVIC_E000E100_NUM_IRQS
+#define CONFIG_NUM_IRQ_PRIO_BITS	ARM_ARMV7M_NVIC_E000E100_NUM_IRQ_PRIO_BITS
+
+#define EXCEPTION_UARTA0		TI_CC32XX_UART_4000C000_IRQ_0
+#define CONFIG_UART_CC32XX_IRQ_PRI	TI_CC32XX_UART_4000C000_ZEPHYR_IRQ_PRIO
+#define UART_CC32XX_BASE_ADDRESS	TI_CC32XX_UART_4000C000_BASE_ADDRESS
+#define CONFIG_UART_CC32XX_BAUDRATE	TI_CC32XX_UART_4000C000_BAUD_RATE
diff --git a/dts/arm/cc32xx_launchxl.dtsi b/dts/arm/cc32xx_launchxl.dtsi
new file mode 100644
index 00000000000..83f8095989f
--- /dev/null
+++ b/dts/arm/cc32xx_launchxl.dtsi
@@ -0,0 +1,52 @@
+#include "armv7-m.dtsi"
+#include <inc/hw_memmap.h>
+#include <inc/hw_ints.h>
+
+/* Note: Zephyr uses exception numbers, vs the IRQ #s used by the CC3200 SDK */
+/* which are offset by 16: */
+#define EXP_UARTA0 (INT_UARTA0 - 16)
+#define EXP_UARTA1 (INT_UARTA1 - 16)
+
+/ {
+	cpus {
+		cpu@0 {
+			compatible = "arm,cortex-m4";
+		};
+	};
+
+	sram0: memory {
+		compatible = "sram";
+		reg = <0x20004000 0x3C000>;
+	};
+
+	flash0: serial-flash {
+		compatible = "serial-flash";
+		reg = <0x0 0x80000>;
+	};
+
+	soc {
+		uart0: uart@UARTA0_BASE {
+			compatible = "ti,cc32xx-uart";
+			reg = <UARTA0_BASE 0x4c>;
+			interrupts = <EXP_UARTA0>;
+			zephyr,irq-prio = <3>;
+			baud-rate = <115200>;
+			status = "disabled";
+		};
+
+		uart1: uart@UARTA1_BASE {
+			compatible = "ti,cc32xx-uart";
+			reg = <UARTA1_BASE 0x4c>;
+			interrupts = <EXP_UARTA1>;
+			zephyr,irq-prio = <3>;
+			baud-rate = <115200>;
+			status = "disabled";
+		};
+
+	};
+};
+
+&nvic {
+	num-irq-prio-bits = <3>;
+	num-irqs = <179>;
+};
diff --git a/dts/arm/yaml/ti,cc32xx-uart.yaml b/dts/arm/yaml/ti,cc32xx-uart.yaml
new file mode 100644
index 00000000000..c45059fb9a2
--- /dev/null
+++ b/dts/arm/yaml/ti,cc32xx-uart.yaml
@@ -0,0 +1,31 @@
+---
+title: TI CC32XX Uart
+id: ti,cc32xx-uart
+version: 0.1
+
+description: >
+    This binding gives a base representation of the TI CC32XX UART
+
+inherits:
+  - !include uart.yaml
+  - !include zephyr_devices.yaml
+
+properties:
+  - compatible:
+      type: string
+      category: required
+      description: compatible strings
+      constraint: "ti,cc32xx-uart"
+
+  - reg:
+      type: array
+      description: mmio register space
+      generation: define
+      category: required
+
+  - interrupts:
+      type: array
+      category: required
+      description: required interrupts
+      generation: define
+...