michaelh/zephyr
1
0
Fork 0
Code Releases Activity

soc: nxp: imx95: enable multi-level interrupts for m7

Browse source 
Enabled multi-level interrupts for m7 since IRQSTEER is used.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
This commit is contained in:
Yangbo Lu 2025-01-15 18:50:35 +08:00 • committed by Benjamin Cabé
commit 3d109d65ee
1 changed files with 29 additions and 1 deletions
Download patch file Download diff file Expand all files Collapse all files

30
soc/nxp/imx/imx9/imx95/Kconfig.defconfig.mimx95.m7
View file

@ -11,8 +11,36 @@ config FLASH_SIZE
config FLASH_BASE_ADDRESS
default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH))
# multi-level interrupts
config MULTI_LEVEL_INTERRUPTS
default y
config 1ST_LEVEL_INTERRUPT_BITS
default 8
config MAX_IRQ_PER_AGGREGATOR
default 16
config 2ND_LEVEL_INTERRUPTS
default y
config 2ND_LVL_ISR_TBL_OFFSET
default 234
config NUM_2ND_LEVEL_AGGREGATORS
default 1
config 2ND_LEVEL_INTERRUPT_BITS
default 8
config 2ND_LVL_INTR_00_OFFSET
default 224
config 3RD_LEVEL_INTERRUPTS
default n
config NUM_IRQS
default 230
default 250 # 2ND_LVL_ISR_TBL_OFFSET + MAX_IRQ_PER_AGGREGATOR * NUM_2ND_LEVEL_AGGREGATORS
config SYS_CLOCK_HW_CYCLES_PER_SEC
default 800000000