dts: bindings: riscv: Add and use bindings for sifive CPUs.

No relevant bindings exist for previous CPU compatible properties, so
add new ones.

Signed-off-by: Shawn Nematbakhsh <shawn@rivosinc.com>

dts/bindings/riscv/riscv,sifive-e31.yaml

@@ -0,0 +1,8 @@
+# Copyright (c) 2022 Shawn Nematbakhsh <shawn@rivosinc.com>
+# SPDX-License-Identifier: Apache-2.0
+
+description: SiFive E31 Standard Core CPU
+
+compatible: "riscv,sifive-e31"
+
+include: riscv,sifive.yaml

dts/bindings/riscv/riscv,sifive-e51.yaml

@@ -0,0 +1,8 @@
+# Copyright (c) 2022 Shawn Nematbakhsh <shawn@rivosinc.com>
+# SPDX-License-Identifier: Apache-2.0
+
+description: SiFive E51 Standard Core CPU
+
+compatible: "riscv,sifive-e51"
+
+include: riscv,sifive.yaml

dts/bindings/riscv/riscv,sifive-s7.yaml

@@ -0,0 +1,8 @@
+# Copyright (c) 2022 Shawn Nematbakhsh <shawn@rivosinc.com>
+# SPDX-License-Identifier: Apache-2.0
+
+description: SiFive S7 Standard Core CPU
+
+compatible: "riscv,sifive-s7"
+
+include: riscv,sifive.yaml

dts/riscv/riscv32-fe310.dtsi

@@ -11,7 +11,7 @@
 		#address-cells = <1>;
 		#size-cells = <0>;
 		cpu: cpu@0 {
-			compatible = "sifive,rocket0", "riscv";
+			compatible = "riscv,sifive-e31";
 			device_type = "cpu";
 			reg = <0>;
 			riscv,isa = "rv32imac";

dts/riscv/riscv64-fu540.dtsi

@@ -17,7 +17,7 @@
 		#size-cells = <0>;
 
 		cpu: cpu@0 {
-			compatible = "sifive,e51", "riscv";
+			compatible = "riscv,sifive-e51";
 			device_type = "cpu";
 			reg = <0>;
 			riscv,isa = "rv64imac";

dts/riscv/riscv64-fu740.dtsi

@@ -17,7 +17,7 @@
 		#size-cells = <0>;
 
 		cpu: cpu@0 {
-			compatible = "sifive,s7", "riscv";
+			compatible = "riscv,sifive-s7";
 			device_type = "cpu";
 			reg = <0>;
 			riscv,isa = "rv64imac";