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dts: bindings: riscv: Add and use bindings for sifive CPUs.

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No relevant bindings exist for previous CPU compatible properties, so
add new ones.

Signed-off-by: Shawn Nematbakhsh <shawn@rivosinc.com>
This commit is contained in:
Shawn Nematbakhsh 2022-03-31 10:42:40 -07:00 • committed by Carles Cufí
commit 3cf0081e60
6 changed files with 27 additions and 3 deletions
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8
dts/bindings/riscv/riscv,sifive-e31.yaml Normal file
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# Copyright (c) 2022 Shawn Nematbakhsh <shawn@rivosinc.com>
# SPDX-License-Identifier: Apache-2.0
description: SiFive E31 Standard Core CPU
compatible: "riscv,sifive-e31"
include: riscv,sifive.yaml

8
dts/bindings/riscv/riscv,sifive-e51.yaml Normal file
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# Copyright (c) 2022 Shawn Nematbakhsh <shawn@rivosinc.com>
# SPDX-License-Identifier: Apache-2.0
description: SiFive E51 Standard Core CPU
compatible: "riscv,sifive-e51"
include: riscv,sifive.yaml

8
dts/bindings/riscv/riscv,sifive-s7.yaml Normal file
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# Copyright (c) 2022 Shawn Nematbakhsh <shawn@rivosinc.com>
# SPDX-License-Identifier: Apache-2.0
description: SiFive S7 Standard Core CPU
compatible: "riscv,sifive-s7"
include: riscv,sifive.yaml