michaelh/zephyr
1
0
Fork 0
Code Releases Activity

tests: kernel: fatal: add MIPS exception comments

Browse source 
We don't use TLB at the moment. Jumping to address 0 (USEG)
leads to TLB exception (instruction fetch).

Division by zero leads to TRAP exception.

Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
This commit is contained in:
Antony Pavlov 2020-12-22 12:15:24 +03:00 • committed by Anas Nashif
commit 3c6d749e49
1 changed files with 2 additions and 2 deletions
Download patch file Download diff file Expand all files Collapse all files

4
tests/kernel/fatal/exception/src/main.c
View file

@ -81,7 +81,7 @@ void entry_cpu_exception(void *p1, void *p2, void *p3)
__asm__ volatile ("swi");
#else
/* Triggers usage fault on ARM, illegal instruction on RISCV
* and xtensa
* and xtensa, TLB exception (instruction fetch) on MIPS.
*/
{
volatile long illegal = 0;
@ -114,7 +114,7 @@ void entry_cpu_exception_extend(void *p1, void *p2, void *p3)
#elif defined(CONFIG_ARC)
__asm__ volatile ("swi");
#else
/* used to create a divide by zero error on X86 */
/* used to create a divide by zero error on X86 and MIPS */
volatile int error;
volatile int zero = 0;