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clock control: clean up after stm32cube LL driver

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After introduction and activation of STM32Cube LL based driver on
F3 and L4 series, this commit removes the no more needed code for
native driver for these soc.

Change-Id: I266d1a3fc4b464cee34b1cc1a1a333c5bf923e41
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This commit is contained in:
Erwan Gouriou 2017-01-25 14:05:19 +01:00 • committed by Maureen Helm
commit 3c389b54f0
12 changed files with 0 additions and 1297 deletions
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11
boards/arm/nucleo_f334r8/nucleo_f334r8_defconfig
View file

@ -55,14 +55,3 @@ CONFIG_CLOCK_STM32_PLL_MULTIPLIER=9
CONFIG_CLOCK_STM32_AHB_PRESCALER=1
CONFIG_CLOCK_STM32_APB1_PRESCALER=2
CONFIG_CLOCK_STM32_APB2_PRESCALER=1
# RCC configuration
CONFIG_CLOCK_CONTROL_STM32F3X=n
CONFIG_CLOCK_CONTROL_STM32F3X_DEVICE_INIT_PRIORITY=1
CONFIG_CLOCK_STM32F3X_SYSCLK_SRC_PLL=y
CONFIG_CLOCK_STM32F3X_PLL_SRC_HSE=y
CONFIG_CLOCK_STM32F3X_PLL_PREDIV=0
CONFIG_CLOCK_STM32F3X_PLL_MULTIPLIER=9
CONFIG_CLOCK_STM32F3X_AHB_PRESCALER=0
CONFIG_CLOCK_STM32F3X_APB1_PRESCALER=2
CONFIG_CLOCK_STM32F3X_APB2_PRESCALER=0

14
boards/arm/nucleo_l476rg/nucleo_l476rg_defconfig
View file

@ -46,20 +46,6 @@ CONFIG_CLOCK_STM32_AHB_PRESCALER=1
CONFIG_CLOCK_STM32_APB1_PRESCALER=1
CONFIG_CLOCK_STM32_APB2_PRESCALER=1
CONFIG_CLOCK_CONTROL_STM32L4X=n
CONFIG_CLOCK_STM32L4X_SYSCLK_SRC_PLL=y
# use 16MHz oscillator
CONFIG_CLOCK_STM32F10X_PLL_SRC_HSI=y
# produce 80MHz clock at PLL output
CONFIG_CLOCK_STM32L4X_PLL_DIVISOR=1
CONFIG_CLOCK_STM32L4X_PLL_MULTIPLIER=20
CONFIG_CLOCK_STM32L4X_PLL_P_DIVISOR=7
CONFIG_CLOCK_STM32L4X_PLL_Q_DIVISOR=2
CONFIG_CLOCK_STM32L4X_PLL_R_DIVISOR=4
CONFIG_CLOCK_STM32L4X_AHB_PRESCALER=0
CONFIG_CLOCK_STM32L4X_APB1_PRESCALER=0
CONFIG_CLOCK_STM32L4X_APB2_PRESCALER=0
# console
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y

11
boards/arm/stm32373c_eval/stm32373c_eval_defconfig
View file

@ -64,14 +64,3 @@ CONFIG_CLOCK_STM32_PLL_MULTIPLIER=9
CONFIG_CLOCK_STM32_AHB_PRESCALER=1
CONFIG_CLOCK_STM32_APB1_PRESCALER=2
CONFIG_CLOCK_STM32_APB2_PRESCALER=2
# RCC configuration
CONFIG_CLOCK_CONTROL_STM32F3X=n
CONFIG_CLOCK_CONTROL_STM32F3X_DEVICE_INIT_PRIORITY=1
CONFIG_CLOCK_STM32F3X_SYSCLK_SRC_PLL=y
CONFIG_CLOCK_STM32F3X_PLL_SRC_HSE=y
CONFIG_CLOCK_STM32F3X_PLL_PREDIV=0
CONFIG_CLOCK_STM32F3X_PLL_MULTIPLIER=9
CONFIG_CLOCK_STM32F3X_AHB_PRESCALER=0
CONFIG_CLOCK_STM32F3X_APB1_PRESCALER=2
CONFIG_CLOCK_STM32F3X_APB2_PRESCALER=2

4
drivers/clock_control/Kconfig
View file

@ -50,12 +50,8 @@ source "drivers/clock_control/Kconfig.stm32f10x"
source "drivers/clock_control/Kconfig.stm32f107xx"
source "drivers/clock_control/Kconfig.stm32f3x"
source "drivers/clock_control/Kconfig.stm32f4x"
source "drivers/clock_control/Kconfig.stm32l4x"
source "drivers/clock_control/Kconfig.beetle"
endif # CLOCK_CONTROL

115
drivers/clock_control/Kconfig.stm32f3x
View file

@ -1,115 +0,0 @@
# Kconfig - STM32F3 MCU clock control driver config
#
# Copyright (c) 2016 RnDity Sp. z o.o.
#
# SPDX-License-Identifier: Apache-2.0
#
if SOC_SERIES_STM32F3X
menuconfig CLOCK_CONTROL_STM32F3X
bool
prompt "STM32F3x Reset & Clock Control"
depends on CLOCK_CONTROL && SOC_SERIES_STM32F3X
default y if SOC_SERIES_STM32F3X
help
Enable driver for Reset & Clock Control subsystem found
in STM32F3 family of MCUs
config CLOCK_CONTROL_STM32F3X_DEVICE_INIT_PRIORITY
int "Clock Control Device Priority"
default 1
depends on CLOCK_CONTROL_STM32F3X
help
This option controls the priority of clock control
device initialization. Higher priority ensures that the device
is initialized earlier in the startup cycle. If unsure, leave
at default value 1
choice
prompt "STM32F3x System Clock Source"
depends on CLOCK_CONTROL_STM32F3X
config CLOCK_STM32F3X_SYSCLK_SRC_HSI
bool "HSI"
help
Use HSI as source of SYSCLK
config CLOCK_STM32F3X_SYSCLK_SRC_HSE
bool "HSE"
help
Use HSE as source of SYSCLK
config CLOCK_STM32F3X_SYSCLK_SRC_PLL
bool "PLL"
help
Use PLL as source of SYSCLK
endchoice
choice
prompt "STM32F3x PLL Clock Source"
depends on CLOCK_CONTROL_STM32F3X && CLOCK_STM32F3X_SYSCLK_SRC_PLL
config CLOCK_STM32F3X_PLL_SRC_HSI
bool "HSI"
help
Use HSI/2 as source of PLL
config CLOCK_STM32F3X_PLL_SRC_HSE
bool "HSE"
help
Use HSE as source of PLL
endchoice
config CLOCK_STM32F3X_HSE_BYPASS
bool "HSE bypass"
depends on CLOCK_CONTROL_STM32F3X && (CLOCK_STM32F3X_PLL_SRC_HSE || CLOCK_STM32F3X_SYSCLK_SRC_HSE)
help
Enable this option to bypass external high-speed clock (HSE).
config CLOCK_STM32F3X_PLL_PREDIV
int "PREDIV1 Prescler"
depends on CLOCK_CONTROL_STM32F3X && CLOCK_STM32F3X_PLL_SRC_HSE
default 0
range 0 16
help
PREDIV is PLLSCR clock signal prescaler, allowed values: 0 - 16.
config CLOCK_STM32F3X_PLL_MULTIPLIER
int "PLL multiplier"
depends on CLOCK_CONTROL_STM32F3X && CLOCK_STM32F3X_SYSCLK_SRC_PLL
default 9
range 2 16
help
PLL multiplier, allowed values: 2-16. PLL output must not exceed 72MHz.
config CLOCK_STM32F3X_AHB_PRESCALER
int "AHB prescaler"
depends on CLOCK_CONTROL_STM32F3X
default 0
range 0 512
help
AHB prescaler, allowed values: 0, 2, 4, 8, 16, 64, 128,
256, 512.
config CLOCK_STM32F3X_APB1_PRESCALER
int "APB1 prescaler"
depends on CLOCK_CONTROL_STM32F3X
default 0
range 0 16
help
APB1 Low speed clock (PCLK1) prescaler, allowed values:
0, 2, 4, 8, 16. The APB1 clock must not exceed 36MHz.
config CLOCK_STM32F3X_APB2_PRESCALER
int "APB2 prescaler"
depends on CLOCK_CONTROL_STM32F3X
default 0
range 0 16
help
APB2 High speed clock (PCLK2) prescaler, allowed values:
0, 2, 4, 8, 16
endif

140
drivers/clock_control/Kconfig.stm32l4x
View file

@ -1,140 +0,0 @@
# Kconfig - STM32L4 MCU clock control driver config
#
# Copyright (c) 2016 Open-RnD Sp. z o.o.
# Copyright (c) 2016 BayLibre, SAS
#
# SPDX-License-Identifier: Apache-2.0
#
if SOC_SERIES_STM32L4X
menuconfig CLOCK_CONTROL_STM32L4X
bool
prompt "STM32L4x Reset & Clock Control"
depends on CLOCK_CONTROL && SOC_SERIES_STM32L4X
default y if SOC_SERIES_STM32L4X
help
Enable driver for Reset & Clock Control subsystem found
in STM32L4 family of MCUs
config CLOCK_CONTROL_STM32L4X_DEVICE_INIT_PRIORITY
int "Clock Control Device Priority"
default 1
depends on CLOCK_CONTROL_STM32L4X
help
This option controls the priority of clock control
device initialization. Higher priority ensures that the device
is initialized earlier in the startup cycle. If unsure, leave
at default value 1
choice
prompt "STM32L4X System Clock Source"
depends on CLOCK_CONTROL_STM32L4X
default CLOCK_STM32L4X_SYSCLK_SRC_PLL
config CLOCK_STM32L4X_SYSCLK_SRC_HSE
bool "HSE"
help
Use HSE as source of SYSCLK
config CLOCK_STM32L4X_SYSCLK_SRC_PLL
bool "PLL"
help
Use PLL as source of SYSCLK
endchoice
choice
prompt "STM32L4X PLL Clock Source"
depends on CLOCK_CONTROL_STM32L4X && CLOCK_STM32L4X_SYSCLK_SRC_PLL
default CLOCK_STM32L4X_PLL_SRC_HSI
config CLOCK_STM32L4X_PLL_SRC_MSI
bool "MSI"
help
Use MSI as source of PLL
config CLOCK_STM32L4X_PLL_SRC_HSI
bool "HSI"
help
Use HSI as source of PLL
endchoice
config CLOCK_STM32L4X_HSE_BYPASS
bool "HSE bypass"
depends on CLOCK_CONTROL_STM32L4X && CLOCK_STM32L4X_SYSCLK_SRC_HSE
help
Enable this option to bypass external high-speed clock (HSE).
config CLOCK_STM32L4X_PLL_DIVISOR
int "PLL divisor"
depends on CLOCK_CONTROL_STM32L4X && CLOCK_STM32L4X_SYSCLK_SRC_PLL
default 1
range 1 8
help
PLL divisor, allowed values: 1-8. With this ensure that the PLL
VCO input frequency ranges from 4 to 16MHz.
config CLOCK_STM32L4X_PLL_MULTIPLIER
int "PLL multiplier"
depends on CLOCK_CONTROL_STM32L4X && CLOCK_STM32L4X_SYSCLK_SRC_PLL
default 20
range 8 86
help
PLL multiplier, allowed values: 2-16. PLL output must not
exceed 344MHz.
config CLOCK_STM32L4X_PLL_P_DIVISOR
int "PLL P Divisor"
depends on CLOCK_CONTROL_STM32L4X
default 7
range 0 17
help
PLL P Output divisor, allowed values: 0, 7, 17.
config CLOCK_STM32L4X_PLL_Q_DIVISOR
int "PLL Q Divisor"
depends on CLOCK_CONTROL_STM32L4X
default 2
range 0 8
help
PLL Q Output divisor, allowed values: 0, 2, 4, 6, 8.
config CLOCK_STM32L4X_PLL_R_DIVISOR
int "PLL R Divisor"
depends on CLOCK_CONTROL_STM32L4X
default 4
range 0 8
help
PLL R Output divisor, allowed values: 0, 2, 4, 6, 8.
config CLOCK_STM32L4X_AHB_PRESCALER
int "AHB prescaler"
depends on CLOCK_CONTROL_STM32L4X
default 0
range 0 512
help
AHB prescaler, allowed values: 0, 2, 4, 8, 16, 64, 128,
256, 512.
config CLOCK_STM32L4X_APB1_PRESCALER
int "APB1 prescaler"
depends on CLOCK_CONTROL_STM32L4X
default 0
range 0 16
help
APB1 Low speed clock (PCLK1) prescaler, allowed values:
0, 2, 4, 8, 16
config CLOCK_STM32L4X_APB2_PRESCALER
int "APB2 prescaler"
depends on CLOCK_CONTROL_STM32L4X
default 0
range 0 16
help
APB2 High speed clock (PCLK2) prescaler, allowed values:
0, 2, 4, 8, 16
endif

2
drivers/clock_control/Makefile
View file

@ -7,8 +7,6 @@ obj-$(CONFIG_SOC_SERIES_STM32F3X) += stm32f3x_ll_clock.o
else
obj-$(CONFIG_CLOCK_CONTROL_STM32F10X) += stm32f10x_clock.o
obj-$(CONFIG_CLOCK_CONTROL_STM32F10X_CONN_LINE) += stm32f107xx_clock.o
obj-$(CONFIG_CLOCK_CONTROL_STM32F3X) += stm32f3x_clock.o
obj-$(CONFIG_CLOCK_CONTROL_STM32F4X) += stm32f4x_clock.o
obj-$(CONFIG_CLOCK_CONTROL_STM32L4X) += stm32l4x_clock.o
endif
obj-$(CONFIG_CLOCK_CONTROL_BEETLE) += beetle_clock_control.o

398
drivers/clock_control/stm32f3x_clock.c
View file

@ -1,398 +0,0 @@
/*
* Copyright (c) 2016 RnDity Sp. z o.o.
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @brief Driver for Reset & Clock Control of STM32F3x family processor.
*
* Based on reference manual:
* STM32F303xB.C.D.E advanced ARM-based 32-bit MCU
* advanced ARM ® -based 32-bit MCUs
*
* Chapter 9: Reset and clock control (RCC)
*
* STM32F334xx advanced ARM ® -based 32-bit MCUs
*
* Chapter 8: Reset and clock control (RCC)
*/
#include <soc.h>
#include <soc_registers.h>
#include <clock_control.h>
#include <misc/util.h>
#include <misc/__assert.h>
#include <clock_control/stm32_clock_control.h>
struct stm32f3x_rcc_data {
uint8_t *base;
};
static int stm32f3x_clock_control_on(struct device *dev,
clock_control_subsys_t sub_system)
{
struct stm32f3x_rcc_data *data = dev->driver_data;
volatile struct stm32f3x_rcc *rcc =
(struct stm32f3x_rcc *)(data->base);
uint32_t subsys = POINTER_TO_UINT(sub_system);
if (subsys > STM32F3X_CLOCK_AHB_BASE) {
subsys &= ~(STM32F3X_CLOCK_AHB_BASE);
rcc->ahbenr |= subsys;
} else if (subsys > STM32F3X_CLOCK_APB2_BASE) {
subsys &= ~(STM32F3X_CLOCK_APB2_BASE);
rcc->apb2enr |= subsys;
} else {
rcc->apb1enr |= subsys;
}
return 0;
}
static int stm32f3x_clock_control_off(struct device *dev,
clock_control_subsys_t sub_system)
{
struct stm32f3x_rcc_data *data = dev->driver_data;
volatile struct stm32f3x_rcc *rcc =
(struct stm32f3x_rcc *)(data->base);
uint32_t subsys = POINTER_TO_UINT(sub_system);
if (subsys > STM32F3X_CLOCK_AHB_BASE) {
subsys &= ~(STM32F3X_CLOCK_AHB_BASE);
rcc->ahbenr &= ~subsys;
} else if (subsys > STM32F3X_CLOCK_APB2_BASE) {
subsys &= ~(STM32F3X_CLOCK_APB2_BASE);
rcc->apb2enr &= ~subsys;
} else {
rcc->apb1enr &= ~subsys;
}
return 0;
}
/**
* @brief helper for mapping a setting to register value
*/
struct regval_map {
int val;
int reg;
};
static int map_reg_val(const struct regval_map *map,
size_t cnt, int val, uint8_t normalize)
{
for (int i = 0; i < cnt; i++) {
if (map[i].val == val) {
return (map[i].reg >> normalize);
}
}
return 0;
}
/**
* @brief map APB prescaler setting to register value
*/
static int apb_prescaler(int prescaler)
{
if (prescaler == 0) {
return RCC_HCLK_DIV1;
}
const struct regval_map map[] = {
{0, RCC_HCLK_DIV1},
{2, RCC_HCLK_DIV2},
{4, RCC_HCLK_DIV4},
{8, RCC_HCLK_DIV8},
{16, RCC_HCLK_DIV16},
};
return map_reg_val(map, ARRAY_SIZE(map),
prescaler, RCC_CFGR_PPRE1_Pos);
}
/**
* @brief map AHB prescaler setting to register value
*/
static int ahb_prescaler(int prescaler)
{
if (prescaler == 0) {
return RCC_SYSCLK_DIV1;
}
const struct regval_map map[] = {
{0, RCC_SYSCLK_DIV1},
{2, RCC_SYSCLK_DIV2},
{4, RCC_SYSCLK_DIV4},
{8, RCC_SYSCLK_DIV8},
{16, RCC_SYSCLK_DIV16},
{64, RCC_SYSCLK_DIV64},
{128, RCC_SYSCLK_DIV128},
{256, RCC_SYSCLK_DIV256},
{512, RCC_SYSCLK_DIV512},
};
return map_reg_val(map, ARRAY_SIZE(map),
prescaler, RCC_CFGR_HPRE_Pos);
}
/**
* @brief map PLL multiplier setting to register value
*/
static int pllmul(int mul)
{
/* x2 -> 0x0
* x3 -> 0x1
* x4 -> 0x2
* ...
* x15 -> 0xd
* x16 -> 0xe
* x16 -> 0xf
*/
return mul - 2;
}
/**
* @brief select PREDIV division factor
*/
static int prediv_prescaler(int prescaler)
{
if (prescaler == 0) {
return RCC_HSE_PREDIV_DIV1;
}
const struct regval_map map[] = {
{0, RCC_HSE_PREDIV_DIV1},
{2, RCC_HSE_PREDIV_DIV2},
{3, RCC_HSE_PREDIV_DIV3},
{4, RCC_HSE_PREDIV_DIV4},
{5, RCC_HSE_PREDIV_DIV5},
{6, RCC_HSE_PREDIV_DIV6},
{7, RCC_HSE_PREDIV_DIV7},
{8, RCC_HSE_PREDIV_DIV8},
{9, RCC_HSE_PREDIV_DIV9},
{10, RCC_HSE_PREDIV_DIV10},
{11, RCC_HSE_PREDIV_DIV11},
{12, RCC_HSE_PREDIV_DIV12},
{13, RCC_HSE_PREDIV_DIV13},
{14, RCC_HSE_PREDIV_DIV14},
{15, RCC_HSE_PREDIV_DIV15},
{16, RCC_HSE_PREDIV_DIV16},
};
return map_reg_val(map, ARRAY_SIZE(map), prescaler, 0);
}
/**
* @brief select System Clock Source
*/
static int system_clock(int source)
{
__ASSERT_NO_MSG(IS_RCC_SYSCLKSOURCE(source));
return (source >> RCC_CFGR_SW_Pos);
}
/**
* @brief select PLL Clock Source
*/
static int pll_source(int source)
{
__ASSERT_NO_MSG(IS_RCC_PLLSOURCE(source));
return (source >> RCC_CFGR_PLLSRC_Pos);
}
static uint32_t get_ahb_clock(uint32_t sysclk)
{
/* AHB clock is generated based on SYSCLK */
uint32_t sysclk_div = CONFIG_CLOCK_STM32F3X_AHB_PRESCALER;
if (sysclk_div == 0) {
sysclk_div = 1;
}
return sysclk / sysclk_div;
}
static uint32_t get_apb_clock(uint32_t ahb_clock, uint32_t prescaler)
{
if (prescaler == 0) {
prescaler = 1;
}
return ahb_clock / prescaler;
}
static
int stm32f3x_clock_control_get_subsys_rate(struct device *clock,
clock_control_subsys_t sub_system,
uint32_t *rate)
{
ARG_UNUSED(clock);
uint32_t subsys = POINTER_TO_UINT(sub_system);
uint32_t prescaler = CONFIG_CLOCK_STM32F3X_APB1_PRESCALER;
/* assumes SYSCLK is SYS_CLOCK_HW_CYCLES_PER_SEC */
uint32_t ahb_clock =
get_ahb_clock(CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC);
if (subsys > STM32F3X_CLOCK_AHB_BASE) {
prescaler = CONFIG_CLOCK_STM32F3X_AHB_PRESCALER;
} else if (subsys > STM32F3X_CLOCK_APB2_BASE) {
prescaler = CONFIG_CLOCK_STM32F3X_APB2_PRESCALER;
}
*rate = get_apb_clock(ahb_clock, prescaler);
return 0;
}
static const struct clock_control_driver_api stm32f3x_clock_control_api = {
.on = stm32f3x_clock_control_on,
.off = stm32f3x_clock_control_off,
.get_rate = stm32f3x_clock_control_get_subsys_rate,
};
/**
* @brief setup embedded flash controller
*
* Configure flash access time latency depending on SYSCLK.
*/
static void setup_flash(void)
{
volatile struct stm32_flash *flash =
(struct stm32_flash *)(FLASH_R_BASE);
if (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC <= 24000000) {
flash->acr.bit.latency = STM32_FLASH_LATENCY_0;
} else if (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC <= 48000000) {
flash->acr.bit.latency = STM32_FLASH_LATENCY_1;
} else if (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC <= 72000000) {
flash->acr.bit.latency = STM32_FLASH_LATENCY_2;
}
}
static int stm32f3x_clock_control_init(struct device *dev)
{
struct stm32f3x_rcc_data *data = dev->driver_data;
volatile struct stm32f3x_rcc *rcc =
(struct stm32f3x_rcc *)(data->base);
/* SYSCLK source defaults to HSI */
int sysclk_src = system_clock(RCC_SYSCLKSOURCE_HSI);
uint32_t hpre = ahb_prescaler(CONFIG_CLOCK_STM32F3X_AHB_PRESCALER);
uint32_t ppre1 = apb_prescaler(CONFIG_CLOCK_STM32F3X_APB1_PRESCALER);
uint32_t ppre2 = apb_prescaler(CONFIG_CLOCK_STM32F3X_APB2_PRESCALER);
#ifdef CONFIG_CLOCK_STM32F3X_PLL_MULTIPLIER
uint32_t pll_mul = pllmul(CONFIG_CLOCK_STM32F3X_PLL_MULTIPLIER);
#endif /* CONFIG_CLOCK_STM32F3X_PLL_MULTIPLIER */
#ifdef CONFIG_CLOCK_STM32F3X_PLL_PREDIV
uint32_t prediv =
prediv_prescaler(CONFIG_CLOCK_STM32F3X_PLL_PREDIV);
#endif /* CONFIG_CLOCK_STM32F3X_PLL_PREDIV */
/* disable PLL */
rcc->cr.bit.pllon = 0;
/* disable HSE */
rcc->cr.bit.hseon = 0;
#ifdef CONFIG_CLOCK_STM32F3X_HSE_BYPASS
/* HSE is disabled, HSE bypass can be enabled*/
rcc->cr.bit.hsebyp = 1;
#endif
#ifdef CONFIG_CLOCK_STM32F3X_PLL_SRC_HSI
/* enable HSI clock */
rcc->cr.bit.hsion = 1;
/* this should end after one test */
while (rcc->cr.bit.hsirdy != 1) {
}
/* HSI clock divided by 2 selected as PLL entry clock source. */
rcc->cfgr.bit.pllsrc = pll_source(RCC_PLLSOURCE_HSI);
#endif /* CONFIG_CLOCK_STM32F3X_PLL_SRC_HSI */
#ifdef CONFIG_CLOCK_STM32F3X_PLL_SRC_HSE
/* wait for to become ready */
rcc->cr.bit.hseon = 1;
while (rcc->cr.bit.hserdy != 1) {
}
#ifdef CONFIG_CLOCK_STM32F3X_PLL_PREDIV
rcc->cfgr2.bit.prediv = prediv;
#endif /* CONFIG_CLOCK_STM32F3X_PLL_PREDIV */
/* HSE clock selected as PLL entry clock source. */
rcc->cfgr.bit.pllsrc = pll_source(RCC_PLLSOURCE_HSE);
#endif /* CONFIG_CLOCK_STM32F3X_PLL_SRC_HSE */
/* setup AHB prescaler */
rcc->cfgr.bit.hpre = hpre;
/* setup APB1, must not exceed 36MHz */
rcc->cfgr.bit.ppre1 = ppre1;
/* setup APB2 */
rcc->cfgr.bit.ppre2 = ppre2;
#ifdef CONFIG_CLOCK_STM32F3X_SYSCLK_SRC_HSI
/* enable HSI clock */
rcc->cr.bit.hsion = 1;
/* this should end after one test */
while (rcc->cr.bit.hsirdy != 1) {
}
sysclk_src = system_clock(RCC_SYSCLKSOURCE_HSI);
#elif defined(CONFIG_CLOCK_STM32F3X_SYSCLK_SRC_PLL)
/* setup PLL multiplication (PLL must be disabled) */
rcc->cfgr.bit.pllmul = pll_mul;
/* enable PLL */
rcc->cr.bit.pllon = 1;
/* wait for PLL to become ready */
while (rcc->cr.bit.pllrdy != 1) {
}
sysclk_src = system_clock(RCC_SYSCLKSOURCE_PLLCLK);
#elif defined(CONFIG_CLOCK_STM32F3X_SYSCLK_SRC_HSE)
/* wait for to become ready */
rcc->cr.bit.hseon = 1;
while (rcc->cr.bit.hserdy != 1) {
}
sysclk_src = system_clock(RCC_SYSCLKSOURCE_HSE);
#endif
/* configure flash access latency before SYSCLK source
* switch
*/
setup_flash();
/* set SYSCLK clock value */
rcc->cfgr.bit.sw = sysclk_src;
/* wait for SYSCLK to switch the source */
while (rcc->cfgr.bit.sws != sysclk_src) {
}
dev->driver_api = &stm32f3x_clock_control_api;
return 0;
}
static struct stm32f3x_rcc_data stm32f3x_rcc_data = {
.base = (uint8_t *)RCC_BASE,
};
/* FIXME: move prescaler/multiplier defines into device config */
/**
* @brief RCC device, note that priority is intentionally set to 1 so
* that the device init runs just after SOC init
*/
DEVICE_INIT(rcc_stm32f3x, STM32_CLOCK_CONTROL_NAME,
&stm32f3x_clock_control_init,
&stm32f3x_rcc_data, NULL,
PRE_KERNEL_1,
CONFIG_CLOCK_CONTROL_STM32F3X_DEVICE_INIT_PRIORITY);

383
drivers/clock_control/stm32l4x_clock.c
View file

@ -1,383 +0,0 @@
/*
* Copyright (c) 2016 Open-RnD Sp. z o.o.
* Copyright (c) 2016 BayLibre, SAS
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @brief Driver for Reset & Clock Control of STM32F10x family processor.
*
* Based on reference manual:
* STM32L4x1, STM32L4x2, STM32L431xx STM32L443xx STM32L433xx, STM32L4x5,
* STM32l4x6
* advanced ARM ® -based 32-bit MCUs
*
* Chapter 7: Low-, medium-, high- and XL-density reset and
* clock control
*/
#include <soc.h>
#include <errno.h>
#include <soc_registers.h>
#include <clock_control.h>
#include <misc/util.h>
#include <clock_control/stm32_clock_control.h>
struct stm32l4x_rcc_data {
uint8_t *base;
};
static inline int stm32l4x_clock_control_on(struct device *dev,
clock_control_subsys_t sub_system)
{
struct stm32l4x_rcc_data *data = dev->driver_data;
volatile struct stm32l4x_rcc *rcc = (struct stm32l4x_rcc *)(data->base);
uint32_t subsys = POINTER_TO_UINT(sub_system);
uint32_t base = STM32L4X_CLOCK_BASE(subsys);
uint32_t bit = 1 << STM32L4X_CLOCK_BIT(subsys);
switch (base) {
case STM32L4X_CLOCK_AHB1_BASE:
rcc->ahb1enr |= bit;
break;
case STM32L4X_CLOCK_AHB2_BASE:
rcc->ahb2enr |= bit;
break;
case STM32L4X_CLOCK_AHB3_BASE:
rcc->ahb3enr |= bit;
break;
case STM32L4X_CLOCK_APB1_1_BASE:
rcc->apb1enr1 |= bit;
break;
case STM32L4X_CLOCK_APB1_2_BASE:
rcc->apb1enr2 |= bit;
break;
case STM32L4X_CLOCK_APB2_BASE:
rcc->apb2enr |= bit;
break;
default:
return -EINVAL;
}
return 0;
}
static inline int stm32l4x_clock_control_off(struct device *dev,
clock_control_subsys_t sub_system)
{
struct stm32l4x_rcc_data *data = dev->driver_data;
volatile struct stm32l4x_rcc *rcc =
(struct stm32l4x_rcc *)(data->base);
uint32_t subsys = POINTER_TO_UINT(sub_system);
uint32_t base = STM32L4X_CLOCK_BASE(subsys);
uint32_t bit = 1 << STM32L4X_CLOCK_BIT(subsys);
switch (base) {
case STM32L4X_CLOCK_AHB1_BASE:
rcc->ahb1enr &= bit;
break;
case STM32L4X_CLOCK_AHB2_BASE:
rcc->ahb2enr &= bit;
break;
case STM32L4X_CLOCK_AHB3_BASE:
rcc->ahb3enr &= bit;
break;
case STM32L4X_CLOCK_APB1_1_BASE:
rcc->apb1enr1 &= bit;
break;
case STM32L4X_CLOCK_APB1_2_BASE:
rcc->apb1enr2 &= bit;
break;
case STM32L4X_CLOCK_APB2_BASE:
rcc->apb2enr &= bit;
break;
default:
return -EINVAL;
}
return 0;
}
/**
* @brief helper for mapping a setting to register value
*/
struct regval_map {
int val;
int reg;
};
static int map_reg_val(const struct regval_map *map, size_t cnt, int val)
{
size_t i;
for (i = 0; i < cnt; i++) {
if (map[i].val == val) {
return map[i].reg;
}
}
return 0;
}
/**
* @brief map APB prescaler setting to register value
*/
static int apb_prescaler(int prescaler)
{
if (prescaler == 0) {
return STM32L4X_RCC_CFG_HCLK_DIV_0;
}
const struct regval_map map[] = {
{0, STM32L4X_RCC_CFG_HCLK_DIV_0},
{2, STM32L4X_RCC_CFG_HCLK_DIV_2},
{4, STM32L4X_RCC_CFG_HCLK_DIV_4},
{8, STM32L4X_RCC_CFG_HCLK_DIV_8},
{16, STM32L4X_RCC_CFG_HCLK_DIV_16},
};
return map_reg_val(map, ARRAY_SIZE(map), prescaler);
}
/**
* @brief map AHB prescaler setting to register value
*/
static int ahb_prescaler(int prescaler)
{
if (prescaler == 0)
return STM32L4X_RCC_CFG_SYSCLK_DIV_0;
const struct regval_map map[] = {
{0, STM32L4X_RCC_CFG_SYSCLK_DIV_0},
{2, STM32L4X_RCC_CFG_SYSCLK_DIV_2},
{4, STM32L4X_RCC_CFG_SYSCLK_DIV_4},
{8, STM32L4X_RCC_CFG_SYSCLK_DIV_8},
{16, STM32L4X_RCC_CFG_SYSCLK_DIV_16},
{64, STM32L4X_RCC_CFG_SYSCLK_DIV_64},
{128, STM32L4X_RCC_CFG_SYSCLK_DIV_128},
{256, STM32L4X_RCC_CFG_SYSCLK_DIV_256},
{512, STM32L4X_RCC_CFG_SYSCLK_DIV_512},
};
return map_reg_val(map, ARRAY_SIZE(map), prescaler);
}
static uint32_t get_ahb_clock(uint32_t sysclk)
{
/* AHB clock is generated based on SYSCLK */
uint32_t sysclk_div = CONFIG_CLOCK_STM32L4X_AHB_PRESCALER;
if (sysclk_div == 0) {
sysclk_div = 1;
}
return sysclk / sysclk_div;
}
static uint32_t get_apb_clock(uint32_t ahb_clock, uint32_t prescaler)
{
if (prescaler == 0) {
prescaler = 1;
}
return ahb_clock / prescaler;
}
static
int stm32l4x_clock_control_get_subsys_rate(struct device *clock,
clock_control_subsys_t sub_system,
uint32_t *rate)
{
ARG_UNUSED(clock);
uint32_t subsys = POINTER_TO_UINT(sub_system);
uint32_t base = STM32L4X_CLOCK_BASE(subsys);
/* assumes SYSCLK is SYS_CLOCK_HW_CYCLES_PER_SEC */
uint32_t ahb_clock =
get_ahb_clock(CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC);
switch (base) {
case STM32L4X_CLOCK_AHB1_BASE:
case STM32L4X_CLOCK_AHB2_BASE:
case STM32L4X_CLOCK_AHB3_BASE:
*rate = ahb_clock;
break;
case STM32L4X_CLOCK_APB1_1_BASE:
case STM32L4X_CLOCK_APB1_2_BASE:
*rate = get_apb_clock(ahb_clock,
CONFIG_CLOCK_STM32L4X_APB1_PRESCALER);
break;
case STM32L4X_CLOCK_APB2_BASE:
*rate = get_apb_clock(ahb_clock,
CONFIG_CLOCK_STM32L4X_APB2_PRESCALER);
break;
default:
return -EINVAL;
}
return 0;
}
static const struct clock_control_driver_api stm32l4x_clock_control_api = {
.on = stm32l4x_clock_control_on,
.off = stm32l4x_clock_control_off,
.get_rate = stm32l4x_clock_control_get_subsys_rate,
};
/**
* @brief setup embedded flash controller
*
* Configure flash access time latency depending on SYSCLK.
*/
static inline void setup_flash(void)
{
volatile struct stm32l4x_flash *flash =
(struct stm32l4x_flash *)(FLASH_R_BASE);
if (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC <= 16000000) {
flash->acr.bit.latency = STM32L4X_FLASH_LATENCY_0;
} else if (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC <= 32000000) {
flash->acr.bit.latency = STM32L4X_FLASH_LATENCY_1;
} else if (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC <= 48000000) {
flash->acr.bit.latency = STM32L4X_FLASH_LATENCY_2;
} else if (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC <= 64000000) {
flash->acr.bit.latency = STM32L4X_FLASH_LATENCY_3;
} else if (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC <= 80000000) {
flash->acr.bit.latency = STM32L4X_FLASH_LATENCY_4;
}
}
static int pllqrdiv(int val)
{
switch (val) {
case 2:
return 0;
case 4:
return 1;
case 6:
return 2;
case 8:
return 3;
}
return 0;
}
static int stm32l4x_clock_control_init(struct device *dev)
{
struct stm32l4x_rcc_data *data = dev->driver_data;
volatile struct stm32l4x_rcc *rcc;
/* SYSCLK source defaults to MSI */
int sysclk_src = STM32L4X_RCC_CFG_SYSCLK_SRC_MSI;
uint32_t hpre = ahb_prescaler(CONFIG_CLOCK_STM32L4X_AHB_PRESCALER);
uint32_t ppre1 = apb_prescaler(CONFIG_CLOCK_STM32L4X_APB1_PRESCALER);
uint32_t ppre2 = apb_prescaler(CONFIG_CLOCK_STM32L4X_APB2_PRESCALER);
#ifdef CONFIG_CLOCK_STM32L4X_SYSCLK_SRC_PLL
uint32_t pllm = CONFIG_CLOCK_STM32L4X_PLL_DIVISOR-1;
uint32_t plln = CONFIG_CLOCK_STM32L4X_PLL_MULTIPLIER;
uint32_t pllpdiv = CONFIG_CLOCK_STM32L4X_PLL_P_DIVISOR;
uint32_t pllqdiv = pllqrdiv(CONFIG_CLOCK_STM32L4X_PLL_Q_DIVISOR);
uint32_t pllrdiv = pllqrdiv(CONFIG_CLOCK_STM32L4X_PLL_R_DIVISOR);
#endif /* CONFIG_CLOCK_STM32L4X_PLL_MULTIPLIER */
rcc = (struct stm32l4x_rcc *)(data->base);
/* disable PLL */
rcc->cr.bit.pllon = 0;
/* disable HSE */
rcc->cr.bit.hseon = 0;
#ifdef CONFIG_CLOCK_STM32L4X_HSE_BYPASS
/* HSE is disabled, HSE bypass can be enabled*/
rcc->cr.bit.hsebyp = 1;
#endif
#ifdef CONFIG_CLOCK_STM32L4X_PLL_SRC_MSI
/* enable MSI clock */
rcc->cr.bit.msion = 1;
/* this should end after one test */
while (rcc->cr.bit.msirdy != 1) {
}
/* PLL input from HSI/2 = 4MHz */
rcc->pllcfgr.bit.pllsrc = STM32L4X_RCC_CFG_PLL_SRC_MSI;
#endif /* CONFIG_CLOCK_STM32L4X_PLL_SRC_MSI */
#ifdef CONFIG_CLOCK_STM32L4X_PLL_SRC_HSI
/* wait for to become ready */
rcc->cr.bit.hsion = 1;
while (rcc->cr.bit.hsirdy != 1) {
}
rcc->pllcfgr.bit.pllsrc = STM32L4X_RCC_CFG_PLL_SRC_HSI;
#endif /* CONFIG_CLOCK_STM32L4X_PLL_SRC_HSI */
/* setup AHB prescaler */
rcc->cfgr.bit.hpre = hpre;
/* setup APB1, must not exceed 36MHz */
rcc->cfgr.bit.ppre1 = ppre1;
/* setup APB2 */
rcc->cfgr.bit.ppre2 = ppre2;
#ifdef CONFIG_CLOCK_STM32L4X_SYSCLK_SRC_PLL
/* setup PLL multiplication and divisor (PLL must be disabled) */
rcc->pllcfgr.bit.pllm = pllm;
rcc->pllcfgr.bit.plln = plln;
/* Setup PLL output divisors */
rcc->pllcfgr.bit.pllp = pllpdiv == 17 ? 1 : 0;
rcc->pllcfgr.bit.pllpen = !!pllpdiv;
rcc->pllcfgr.bit.pllq = pllqdiv;
rcc->pllcfgr.bit.pllqen = !!CONFIG_CLOCK_STM32L4X_PLL_Q_DIVISOR;
rcc->pllcfgr.bit.pllr = pllrdiv;
rcc->pllcfgr.bit.pllren = !!CONFIG_CLOCK_STM32L4X_PLL_R_DIVISOR;
/* enable PLL */
rcc->cr.bit.pllon = 1;
/* wait for PLL to become ready */
while (rcc->cr.bit.pllrdy != 1) {
}
sysclk_src = STM32L4X_RCC_CFG_SYSCLK_SRC_PLL;
#elif defined(CONFIG_CLOCK_STM32L4X_SYSCLK_SRC_HSE)
/* wait for to become ready */
rcc->cr.bit.hseon = 1;
while (rcc->cr.bit.hserdy != 1) {
}
sysclk_src = STM32L4X_RCC_CFG_SYSCLK_SRC_HSE;
#else
#error "Need to select or implement support for this STM32L4X SYSCLK source"
#endif
/* configure flash access latency before SYSCLK source
* switch
*/
setup_flash();
/* set SYSCLK clock value */
rcc->cfgr.bit.sw = sysclk_src;
/* wait for SYSCLK to switch the source */
while (rcc->cfgr.bit.sws != sysclk_src) {
}
return 0;
}
static struct stm32l4x_rcc_data stm32l4x_rcc_data = {
.base = (uint8_t *)RCC_BASE,
};
/**
* @brief RCC device, note that priority is intentionally set to 1 so
* that the device init runs just after SOC init
*/
DEVICE_AND_API_INIT(rcc_stm32l4x, STM32_CLOCK_CONTROL_NAME,
&stm32l4x_clock_control_init,
&stm32l4x_rcc_data, NULL,
PRE_KERNEL_1,
CONFIG_CLOCK_CONTROL_STM32L4X_DEVICE_INIT_PRIORITY,
&stm32l4x_clock_control_api);

4
include/drivers/clock_control/stm32_clock_control.h
View file

@ -16,12 +16,8 @@
#ifdef CONFIG_SOC_SERIES_STM32F1X
#include "stm32f1_clock_control.h"
#elif CONFIG_SOC_SERIES_STM32F3X
#include "stm32f3_clock_control.h"
#elif CONFIG_SOC_SERIES_STM32F4X
#include "stm32f4_clock_control.h"
#elif CONFIG_SOC_SERIES_STM32L4X
#include "stm32l4x_clock_control.h"
#endif
/* Bus */

114
include/drivers/clock_control/stm32f3_clock_control.h
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@ -1,114 +0,0 @@
/*
* Copyright (c) 2016 RnDity Sp. z o.o.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _STM32F3_CLOCK_CONTROL_H_
#define _STM32F3_CLOCK_CONTROL_H_
/**
* @file
*
* @brief Clock subsystem IDs for STM32F3 family
*/
/* APB1 */
#define STM32F3X_CLOCK_SUBSYS_TIM2 (1 << 0)
#define STM32F3X_CLOCK_SUBSYS_TIM3 (1 << 1)
#ifndef CONFIG_SOC_STM32F334X8
#define STM32F3X_CLOCK_SUBSYS_TIM4 (1 << 2)
#endif
#ifdef CONFIG_SOC_STM32F373XC
#define STM32F3X_CLOCK_SUBSYS_TIM5 (1 << 3)
#endif
#define STM32F3X_CLOCK_SUBSYS_TIM6 (1 << 4)
#define STM32F3X_CLOCK_SUBSYS_TIM7 (1 << 5)
#ifdef CONFIG_SOC_STM32F373XC
#define STM32F3X_CLOCK_SUBSYS_TIM12 (1 << 6)
#define STM32F3X_CLOCK_SUBSYS_TIM13 (1 << 7)
#define STM32F3X_CLOCK_SUBSYS_TIM14 (1 << 8)
#define STM32F3X_CLOCK_SUBSYS_TIM18 (1 << 9)
#endif
#define STM32F3X_CLOCK_SUBSYS_WWDG (1 << 11)
#ifndef CONFIG_SOC_STM32F334X8
#define STM32F3X_CLOCK_SUBSYS_SPI2 (1 << 14)
#define STM32F3X_CLOCK_SUBSYS_SPI3 (1 << 15)
#endif
#define STM32F3X_CLOCK_SUBSYS_USART2 (1 << 17)
#define STM32F3X_CLOCK_SUBSYS_USART3 (1 << 18)
#ifndef CONFIG_SOC_STM32F334X8
#define STM32F3X_CLOCK_SUBSYS_UART4 (1 << 19)
#define STM32F3X_CLOCK_SUBSYS_UART5 (1 << 20)
#endif
#define STM32F3X_CLOCK_SUBSYS_I2C1 (1 << 21)
#ifndef CONFIG_SOC_STM32F334X8
#define STM32F3X_CLOCK_SUBSYS_I2C2 (1 << 22)
#define STM32F3X_CLOCK_SUBSYS_USB (1 << 23)
#endif
#define STM32F3X_CLOCK_SUBSYS_CAN (1 << 25)
#define STM32F3X_CLOCK_SUBSYS_DAC2 (1 << 26)
#define STM32F3X_CLOCK_SUBSYS_PWR (1 << 28)
#define STM32F3X_CLOCK_SUBSYS_DAC1 (1 << 29)
#define STM32F3X_CLOCK_APB2_BASE (1 << 30)
/* APB2 */
#define STM32F3X_CLOCK_SUBSYS_SYSCFG (STM32F3X_CLOCK_APB2_BASE | 1 << 0)
#ifndef CONFIG_SOC_STM32F373XC
#define STM32F3X_CLOCK_SUBSYS_TIM1 (STM32F3X_CLOCK_APB2_BASE | 1 << 11)
#endif
#define STM32F3X_CLOCK_SUBSYS_SPI1 (STM32F3X_CLOCK_APB2_BASE | 1 << 12)
#ifdef CONFIG_SOC_STM32F303XC
#define STM32F3X_CLOCK_SUBSYS_TIM8 (STM32F3X_CLOCK_APB2_BASE | 1 << 13)
#endif
#define STM32F3X_CLOCK_SUBSYS_USART1 (STM32F3X_CLOCK_APB2_BASE | 1 << 14)
#ifndef CONFIG_SOC_STM32F334X8
#define STM32F3X_CLOCK_SUBSYS_SPI4 (STM32F3X_CLOCK_APB2_BASE | 1 << 15)
#endif
#define STM32F3X_CLOCK_SUBSYS_TIM15 (STM32F3X_CLOCK_APB2_BASE | 1 << 16)
#define STM32F3X_CLOCK_SUBSYS_TIM16 (STM32F3X_CLOCK_APB2_BASE | 1 << 17)
#define STM32F3X_CLOCK_SUBSYS_TIM17 (STM32F3X_CLOCK_APB2_BASE | 1 << 18)
#ifndef CONFIG_SOC_STM32F334X8
#define STM32F3X_CLOCK_SUBSYS_TIM19 (STM32F3X_CLOCK_APB2_BASE | 1 << 19)
#endif
#ifdef CONFIG_SOC_STM32F303XC
#define STM32F3X_CLOCK_SUBSYS_TIM20 (STM32F3X_CLOCK_APB2_BASE | 1 << 20)
#endif
#ifdef CONFIG_SOC_STM32F334X8
#define STM32F3X_CLOCK_SUBSYS_HRTIMER1 (STM32F3X_CLOCK_APB2_BASE | 1 << 29)
#endif
#define STM32F3X_CLOCK_AHB_BASE (1 << 31)
/* AHB */
#define STM32F3X_CLOCK_SUBSYS_DMA1 (STM32F3X_CLOCK_AHB_BASE | 1 << 0)
#ifndef CONFIG_SOC_STM32F334X8
#define STM32F3X_CLOCK_SUBSYS_DMA2 (STM32F3X_CLOCK_AHB_BASE | 1 << 1)
#endif
#define STM32F3X_CLOCK_SUBSYS_SRAM (STM32F3X_CLOCK_AHB_BASE | 1 << 2)
#define STM32F3X_CLOCK_SUBSYS_FLITF (STM32F3X_CLOCK_AHB_BASE | 1 << 4)
#ifndef CONFIG_SOC_STM32F334X8
#define STM32F3X_CLOCK_SUBSYS_FMC (STM32F3X_CLOCK_AHB_BASE | 1 << 5)
#endif
#define STM32F3X_CLOCK_SUBSYS_CRC (STM32F3X_CLOCK_AHB_BASE | 1 << 6)
#ifndef CONFIG_SOC_STM32F334X8
#define STM32F3X_CLOCK_SUBSYS_IOPH (STM32F3X_CLOCK_AHB_BASE | 1 << 16)
#endif
#define STM32F3X_CLOCK_SUBSYS_IOPA (STM32F3X_CLOCK_AHB_BASE | 1 << 17)
#define STM32F3X_CLOCK_SUBSYS_IOPB (STM32F3X_CLOCK_AHB_BASE | 1 << 18)
#define STM32F3X_CLOCK_SUBSYS_IOPC (STM32F3X_CLOCK_AHB_BASE | 1 << 19)
#define STM32F3X_CLOCK_SUBSYS_IOPD (STM32F3X_CLOCK_AHB_BASE | 1 << 20)
#ifndef CONFIG_SOC_STM32F334X8
#define STM32F3X_CLOCK_SUBSYS_IOPE (STM32F3X_CLOCK_AHB_BASE | 1 << 21)
#endif
#define STM32F3X_CLOCK_SUBSYS_IOPF (STM32F3X_CLOCK_AHB_BASE | 1 << 22)
#ifndef CONFIG_SOC_STM32F334X8
#define STM32F3X_CLOCK_SUBSYS_IOPG (STM32F3X_CLOCK_AHB_BASE | 1 << 23)
#endif
#define STM32F3X_CLOCK_SUBSYS_TSC (STM32F3X_CLOCK_AHB_BASE | 1 << 24)
#define STM32F3X_CLOCK_SUBSYS_ADC12 (STM32F3X_CLOCK_AHB_BASE | 1 << 28)
#ifndef CONFIG_SOC_STM32F334X8
#define STM32F3X_CLOCK_SUBSYS_ADC34 (STM32F3X_CLOCK_AHB_BASE | 1 << 29)
#endif
#endif /* _STM32F3_CLOCK_CONTROL_H_ */

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include/drivers/clock_control/stm32l4x_clock_control.h
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@ -1,101 +0,0 @@
/*
* Copyright (c) 2016 Open-RnD Sp. z o.o.
* Copyright (c) 2016 BayLibre, SAS
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _STM32L4X_CLOCK_CONTROL_H_
#define _STM32L4X_CLOCK_CONTROL_H_
/**
* @file
*
* @brief Clock subsystem IDs for STM32L4 family
*/
enum {
STM32L4X_CLOCK_AHB1_BASE = 0,
STM32L4X_CLOCK_AHB2_BASE,
STM32L4X_CLOCK_AHB3_BASE,
STM32L4X_CLOCK_APB1_1_BASE,
STM32L4X_CLOCK_APB1_2_BASE,
STM32L4X_CLOCK_APB2_BASE,
STM32L4X_CLOCK_BASE_COUNT,
};
#define STM32L4X_CLOCK_ID(_base, id) \
((STM32L4X_CLOCK_##_base##_BASE << 16) + id)
#define STM32L4X_CLOCK_BASE(num) ((num) >> 16)
#define STM32L4X_CLOCK_BIT(num) ((num) & 0xFFFF)
enum {
/* AHB1 */
STM32L4X_CLOCK_SUBSYS_DMA1 = STM32L4X_CLOCK_ID(AHB1, 0),
STM32L4X_CLOCK_SUBSYS_DMA2 = STM32L4X_CLOCK_ID(AHB1, 1),
STM32L4X_CLOCK_SUBSYS_FLASH = STM32L4X_CLOCK_ID(AHB1, 8),
STM32L4X_CLOCK_SUBSYS_CRC = STM32L4X_CLOCK_ID(AHB1, 12),
STM32L4X_CLOCK_SUBSYS_TSC = STM32L4X_CLOCK_ID(AHB1, 16),
/* AHB2 */
STM32L4X_CLOCK_SUBSYS_GPIOA = STM32L4X_CLOCK_ID(AHB2, 0),
STM32L4X_CLOCK_SUBSYS_GPIOB = STM32L4X_CLOCK_ID(AHB2, 1),
STM32L4X_CLOCK_SUBSYS_GPIOC = STM32L4X_CLOCK_ID(AHB2, 2),
STM32L4X_CLOCK_SUBSYS_GPIOD = STM32L4X_CLOCK_ID(AHB2, 3),
STM32L4X_CLOCK_SUBSYS_GPIOE = STM32L4X_CLOCK_ID(AHB2, 4),
STM32L4X_CLOCK_SUBSYS_GPIOF = STM32L4X_CLOCK_ID(AHB2, 5),
STM32L4X_CLOCK_SUBSYS_GPIOG = STM32L4X_CLOCK_ID(AHB2, 6),
STM32L4X_CLOCK_SUBSYS_GPIOH = STM32L4X_CLOCK_ID(AHB2, 7),
STM32L4X_CLOCK_SUBSYS_OTGFS = STM32L4X_CLOCK_ID(AHB2, 12),
STM32L4X_CLOCK_SUBSYS_ADC = STM32L4X_CLOCK_ID(AHB2, 13),
STM32L4X_CLOCK_SUBSYS_AES = STM32L4X_CLOCK_ID(AHB2, 16),
STM32L4X_CLOCK_SUBSYS_RNG = STM32L4X_CLOCK_ID(AHB2, 18),
/* AHB3 */
STM32L4X_CLOCK_SUBSYS_FMC = STM32L4X_CLOCK_ID(AHB3, 0),
STM32L4X_CLOCK_SUBSYS_QSPI = STM32L4X_CLOCK_ID(AHB3, 0),
/* APB1 */
STM32L4X_CLOCK_SUBSYS_TIM2 = STM32L4X_CLOCK_ID(APB1_1, 0),
STM32L4X_CLOCK_SUBSYS_TIM3 = STM32L4X_CLOCK_ID(APB1_1, 1),
STM32L4X_CLOCK_SUBSYS_TIM4 = STM32L4X_CLOCK_ID(APB1_1, 2),
STM32L4X_CLOCK_SUBSYS_TIM5 = STM32L4X_CLOCK_ID(APB1_1, 3),
STM32L4X_CLOCK_SUBSYS_TIM6 = STM32L4X_CLOCK_ID(APB1_1, 4),
STM32L4X_CLOCK_SUBSYS_TIM7 = STM32L4X_CLOCK_ID(APB1_1, 5),
STM32L4X_CLOCK_SUBSYS_LCD = STM32L4X_CLOCK_ID(APB1_1, 9),
STM32L4X_CLOCK_SUBSYS_WWDG = STM32L4X_CLOCK_ID(APB1_1, 11),
STM32L4X_CLOCK_SUBSYS_SPI2 = STM32L4X_CLOCK_ID(APB1_1, 14),
STM32L4X_CLOCK_SUBSYS_SPI3 = STM32L4X_CLOCK_ID(APB1_1, 15),
STM32L4X_CLOCK_SUBSYS_USART2 = STM32L4X_CLOCK_ID(APB1_1, 17),
STM32L4X_CLOCK_SUBSYS_USART3 = STM32L4X_CLOCK_ID(APB1_1, 18),
STM32L4X_CLOCK_SUBSYS_UART4 = STM32L4X_CLOCK_ID(APB1_1, 19),
STM32L4X_CLOCK_SUBSYS_UART5 = STM32L4X_CLOCK_ID(APB1_1, 20),
STM32L4X_CLOCK_SUBSYS_I2C1 = STM32L4X_CLOCK_ID(APB1_1, 21),
STM32L4X_CLOCK_SUBSYS_I2C2 = STM32L4X_CLOCK_ID(APB1_1, 22),
STM32L4X_CLOCK_SUBSYS_I2C3 = STM32L4X_CLOCK_ID(APB1_1, 23),
STM32L4X_CLOCK_SUBSYS_PWR = STM32L4X_CLOCK_ID(APB1_1, 28),
STM32L4X_CLOCK_SUBSYS_DAC = STM32L4X_CLOCK_ID(APB1_1, 29),
STM32L4X_CLOCK_SUBSYS_OPAMP = STM32L4X_CLOCK_ID(APB1_1, 30),
STM32L4X_CLOCK_SUBSYS_LPTIM1 = STM32L4X_CLOCK_ID(APB1_1, 31),
STM32L4X_CLOCK_SUBSYS_LPUART1 = STM32L4X_CLOCK_ID(APB1_2, 0),
STM32L4X_CLOCK_SUBSYS_SWPMI1 = STM32L4X_CLOCK_ID(APB1_2, 2),
STM32L4X_CLOCK_SUBSYS_LPTIM2 = STM32L4X_CLOCK_ID(APB1_2, 5),
/* APB2 */
STM32L4X_CLOCK_SUBSYS_SYSCFG = STM32L4X_CLOCK_ID(APB2, 0),
STM32L4X_CLOCK_SUBSYS_FW = STM32L4X_CLOCK_ID(APB2, 7),
STM32L4X_CLOCK_SUBSYS_SDMMC1 = STM32L4X_CLOCK_ID(APB2, 10),
STM32L4X_CLOCK_SUBSYS_TIM1 = STM32L4X_CLOCK_ID(APB2, 11),
STM32L4X_CLOCK_SUBSYS_SPI1 = STM32L4X_CLOCK_ID(APB2, 12),
STM32L4X_CLOCK_SUBSYS_TIM8 = STM32L4X_CLOCK_ID(APB2, 13),
STM32L4X_CLOCK_SUBSYS_USART1 = STM32L4X_CLOCK_ID(APB2, 14),
STM32L4X_CLOCK_SUBSYS_TIM15 = STM32L4X_CLOCK_ID(APB2, 16),
STM32L4X_CLOCK_SUBSYS_TIM16 = STM32L4X_CLOCK_ID(APB2, 17),
STM32L4X_CLOCK_SUBSYS_TIM17 = STM32L4X_CLOCK_ID(APB2, 18),
STM32L4X_CLOCK_SUBSYS_SAI1 = STM32L4X_CLOCK_ID(APB2, 21),
STM32L4X_CLOCK_SUBSYS_SAI2 = STM32L4X_CLOCK_ID(APB2, 22),
STM32L4X_CLOCK_SUBSYS_DFSDM1 = STM32L4X_CLOCK_ID(APB2, 24),
};
#endif /* _STM32L4_CLOCK_CONTROL_H_ */