diff --git a/boards/arm/qemu_cortex_m3/qemu_cortex_m3.dts b/boards/arm/qemu_cortex_m3/qemu_cortex_m3.dts index b0f4a74bfcf..cf29656a491 100644 --- a/boards/arm/qemu_cortex_m3/qemu_cortex_m3.dts +++ b/boards/arm/qemu_cortex_m3/qemu_cortex_m3.dts @@ -41,3 +41,31 @@ ð { status = "ok"; }; + +&gpio0 { + status = "ok"; +}; + +&gpio1 { + status = "ok"; +}; + +&gpio2 { + status = "ok"; +}; + +&gpio3 { + status = "ok"; +}; + +&gpio4 { + status = "ok"; +}; + +&gpio5 { + status = "ok"; +}; + +&gpio6 { + status = "ok"; +}; diff --git a/boards/arm/qemu_cortex_m3/qemu_cortex_m3_defconfig b/boards/arm/qemu_cortex_m3/qemu_cortex_m3_defconfig index 9a2ed54c634..8d99f28d38b 100644 --- a/boards/arm/qemu_cortex_m3/qemu_cortex_m3_defconfig +++ b/boards/arm/qemu_cortex_m3/qemu_cortex_m3_defconfig @@ -8,3 +8,5 @@ CONFIG_SERIAL=y CONFIG_CORTEX_M_SYSTICK=y CONFIG_UART_STELLARIS=y CONFIG_SCHED_MULTIQ=y +CONFIG_GPIO=y +CONFIG_GPIO_STELLARIS=y diff --git a/dts/arm/ti/lm3s6965.dtsi b/dts/arm/ti/lm3s6965.dtsi index fa4dbe7bf70..0cb748c8978 100644 --- a/dts/arm/ti/lm3s6965.dtsi +++ b/dts/arm/ti/lm3s6965.dtsi @@ -56,6 +56,69 @@ local-mac-address = [00 00 94 00 83 00]; label = "ETH"; }; + + gpio0: gpio@40004000 { + compatible = "ti,stellaris-gpio"; + reg = <0x40004000 0x1000>; + interrupts = <0 3>; + label = "GPIO_A"; + gpio-controller; + #gpio-cells = <2>; + }; + + gpio1: gpio@40005000 { + compatible = "ti,stellaris-gpio"; + reg = <0x40005000 0x1000>; + interrupts = <1 3>; + label = "GPIO_B"; + gpio-controller; + #gpio-cells = <2>; + }; + + gpio2: gpio@40006000 { + compatible = "ti,stellaris-gpio"; + reg = <0x40006000 0x1000>; + interrupts = <2 3>; + label = "GPIO_C"; + gpio-controller; + #gpio-cells = <2>; + }; + + gpio3: gpio@40007000 { + compatible = "ti,stellaris-gpio"; + reg = <0x40007000 0x1000>; + interrupts = <3 3>; + label = "GPIO_D"; + gpio-controller; + #gpio-cells = <2>; + }; + + gpio4: gpio@40024000 { + compatible = "ti,stellaris-gpio"; + reg = <0x40024000 0x1000>; + interrupts = <4 3>; + label = "GPIO_E"; + gpio-controller; + #gpio-cells = <2>; + }; + + gpio5: gpio@40025000 { + compatible = "ti,stellaris-gpio"; + reg = <0x40025000 0x1000>; + interrupts = <30 3>; + label = "GPIO_F"; + gpio-controller; + #gpio-cells = <2>; + }; + + gpio6: gpio@40026000 { + compatible = "ti,stellaris-gpio"; + reg = <0x40026000 0x1000>; + interrupts = <31 3>; + label = "GPIO_G"; + gpio-controller; + #gpio-cells = <2>; + }; }; }; diff --git a/dts/bindings/gpio/ti,stellaris-gpio.yaml b/dts/bindings/gpio/ti,stellaris-gpio.yaml new file mode 100644 index 00000000000..a68abd41573 --- /dev/null +++ b/dts/bindings/gpio/ti,stellaris-gpio.yaml @@ -0,0 +1,38 @@ +--- +# SPDX-License-Identifier: Apache-2.0 +title: TI Stellaris GPIO +version: 0.1 + +description: > + This is a representation of the TI Stellaris GPIO node + +properties: + compatible: + type: string + category: required + description: compatible strings + constraint: "ti,stellaris-gpio" + generation: define + + reg: + type: int + description: mmio register space + generation: define + category: required + + label: + type: string + category: required + description: Human readable string describing the device (used by Zephyr for API name) + generation: define + + interrupts: + type: compound + category: required + description: required interrupts + generation: define + +"#cells": + - pin + - flags +... diff --git a/soc/arm/ti_lm3s6965/dts_fixup.h b/soc/arm/ti_lm3s6965/dts_fixup.h index 514f9e2e415..a1abf1f5235 100644 --- a/soc/arm/ti_lm3s6965/dts_fixup.h +++ b/soc/arm/ti_lm3s6965/dts_fixup.h @@ -1,15 +1,50 @@ /* SoC level DTS fixup file */ -#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS -#define DT_ETH_BASE_ADDR DT_TI_STELLARIS_ETHERNET_40048000_BASE_ADDRESS -#define DT_ETH_DRV_NAME DT_TI_STELLARIS_ETHERNET_40048000_LABEL -#define DT_ETH_IRQ DT_TI_STELLARIS_ETHERNET_40048000_IRQ_0 -#define DT_ETH_IRQ_PRIO DT_TI_STELLARIS_ETHERNET_40048000_IRQ_0_PRIORITY -#define DT_ETH_MAC_ADDR_0 DT_TI_STELLARIS_ETHERNET_40048000_LOCAL_MAC_ADDRESS_0 -#define DT_ETH_MAC_ADDR_1 DT_TI_STELLARIS_ETHERNET_40048000_LOCAL_MAC_ADDRESS_1 -#define DT_ETH_MAC_ADDR_2 DT_TI_STELLARIS_ETHERNET_40048000_LOCAL_MAC_ADDRESS_2 -#define DT_ETH_MAC_ADDR_3 DT_TI_STELLARIS_ETHERNET_40048000_LOCAL_MAC_ADDRESS_3 -#define DT_ETH_MAC_ADDR_4 DT_TI_STELLARIS_ETHERNET_40048000_LOCAL_MAC_ADDRESS_4 -#define DT_ETH_MAC_ADDR_5 DT_TI_STELLARIS_ETHERNET_40048000_LOCAL_MAC_ADDRESS_5 +#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS +#define DT_ETH_BASE_ADDR DT_TI_STELLARIS_ETHERNET_40048000_BASE_ADDRESS +#define DT_ETH_DRV_NAME DT_TI_STELLARIS_ETHERNET_40048000_LABEL +#define DT_ETH_IRQ DT_TI_STELLARIS_ETHERNET_40048000_IRQ_0 +#define DT_ETH_IRQ_PRIO DT_TI_STELLARIS_ETHERNET_40048000_IRQ_0_PRIORITY +#define DT_ETH_MAC_ADDR_0 DT_TI_STELLARIS_ETHERNET_40048000_LOCAL_MAC_ADDRESS_0 +#define DT_ETH_MAC_ADDR_1 DT_TI_STELLARIS_ETHERNET_40048000_LOCAL_MAC_ADDRESS_1 +#define DT_ETH_MAC_ADDR_2 DT_TI_STELLARIS_ETHERNET_40048000_LOCAL_MAC_ADDRESS_2 +#define DT_ETH_MAC_ADDR_3 DT_TI_STELLARIS_ETHERNET_40048000_LOCAL_MAC_ADDRESS_3 +#define DT_ETH_MAC_ADDR_4 DT_TI_STELLARIS_ETHERNET_40048000_LOCAL_MAC_ADDRESS_4 +#define DT_ETH_MAC_ADDR_5 DT_TI_STELLARIS_ETHERNET_40048000_LOCAL_MAC_ADDRESS_5 + +#define DT_GPIO_A_BASE_ADDRESS DT_TI_STELLARIS_GPIO_40004000_BASE_ADDRESS +#define DT_GPIO_A_LABEL DT_TI_STELLARIS_GPIO_40004000_LABEL +#define DT_GPIO_A_IRQ DT_TI_STELLARIS_GPIO_40004000_IRQ_0 +#define DT_GPIO_A_IRQ_PRIO DT_TI_STELLARIS_GPIO_40004000_IRQ_0_PRIORITY + +#define DT_GPIO_B_BASE_ADDRESS DT_TI_STELLARIS_GPIO_40005000_BASE_ADDRESS +#define DT_GPIO_B_LABEL DT_TI_STELLARIS_GPIO_40005000_LABEL +#define DT_GPIO_B_IRQ DT_TI_STELLARIS_GPIO_40005000_IRQ_0 +#define DT_GPIO_B_IRQ_PRIO DT_TI_STELLARIS_GPIO_40005000_IRQ_0_PRIORITY + +#define DT_GPIO_C_BASE_ADDRESS DT_TI_STELLARIS_GPIO_40006000_BASE_ADDRESS +#define DT_GPIO_C_LABEL DT_TI_STELLARIS_GPIO_40006000_LABEL +#define DT_GPIO_C_IRQ DT_TI_STELLARIS_GPIO_40006000_IRQ_0 +#define DT_GPIO_C_IRQ_PRIO DT_TI_STELLARIS_GPIO_40006000_IRQ_0_PRIORITY + +#define DT_GPIO_D_BASE_ADDRESS DT_TI_STELLARIS_GPIO_40007000_BASE_ADDRESS +#define DT_GPIO_D_LABEL DT_TI_STELLARIS_GPIO_40007000_LABEL +#define DT_GPIO_D_IRQ DT_TI_STELLARIS_GPIO_40007000_IRQ_0 +#define DT_GPIO_D_IRQ_PRIO DT_TI_STELLARIS_GPIO_40007000_IRQ_0_PRIORITY + +#define DT_GPIO_E_BASE_ADDRESS DT_TI_STELLARIS_GPIO_40024000_BASE_ADDRESS +#define DT_GPIO_E_LABEL DT_TI_STELLARIS_GPIO_40024000_LABEL +#define DT_GPIO_E_IRQ DT_TI_STELLARIS_GPIO_40024000_IRQ_0 +#define DT_GPIO_E_IRQ_PRIO DT_TI_STELLARIS_GPIO_40024000_IRQ_0_PRIORITY + +#define DT_GPIO_F_BASE_ADDRESS DT_TI_STELLARIS_GPIO_40025000_BASE_ADDRESS +#define DT_GPIO_F_LABEL DT_TI_STELLARIS_GPIO_40025000_LABEL +#define DT_GPIO_F_IRQ DT_TI_STELLARIS_GPIO_40025000_IRQ_0 +#define DT_GPIO_F_IRQ_PRIO DT_TI_STELLARIS_GPIO_40025000_IRQ_0_PRIORITY + +#define DT_GPIO_G_BASE_ADDRESS DT_TI_STELLARIS_GPIO_40026000_BASE_ADDRESS +#define DT_GPIO_G_LABEL DT_TI_STELLARIS_GPIO_40026000_LABEL +#define DT_GPIO_G_IRQ DT_TI_STELLARIS_GPIO_40026000_IRQ_0 +#define DT_GPIO_G_IRQ_PRIO DT_TI_STELLARIS_GPIO_40026000_IRQ_0_PRIORITY /* End of SoC Level DTS fixup file */