diff --git a/boards/xtensa/esp32/Kconfig.board b/boards/xtensa/esp32/Kconfig.board index 0294713a218..b0b259a8d33 100644 --- a/boards/xtensa/esp32/Kconfig.board +++ b/boards/xtensa/esp32/Kconfig.board @@ -6,3 +6,4 @@ config BOARD_ESP32 bool "ESP32 Development Board" depends on SOC_ESP32 + select HAS_DTS diff --git a/boards/xtensa/esp32/esp32.dts b/boards/xtensa/esp32/esp32.dts new file mode 100644 index 00000000000..324a4f26b59 --- /dev/null +++ b/boards/xtensa/esp32/esp32.dts @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2019 Intel Corporation. + * + * SPDX-License-Identifier: Apache-2.0 + */ +/dts-v1/; + +#include "esp32.dtsi" + +/ { + model = "esp32"; + compatible = "xtensa,esp32"; + + aliases { + uart-0 = &uart0; + }; + + chosen { + zephyr,sram = &sram0; + zephyr,console = &uart0; + }; +}; + +&uart0 { + status = "ok"; + current-speed = <115200>; +}; diff --git a/boards/xtensa/esp32/esp32_defconfig b/boards/xtensa/esp32/esp32_defconfig index c068def7303..2b461ec53ae 100644 --- a/boards/xtensa/esp32/esp32_defconfig +++ b/boards/xtensa/esp32/esp32_defconfig @@ -11,7 +11,6 @@ CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=40000000 CONFIG_CONSOLE=y CONFIG_SERIAL_HAS_DRIVER=y CONFIG_SERIAL=y -CONFIG_UART_CONSOLE_ON_DEV_NAME="ROMUART" CONFIG_UART_CONSOLE=y CONFIG_UART_ESP32=y diff --git a/dts/bindings/serial/xtensa,esp32-uart.yaml b/dts/bindings/serial/xtensa,esp32-uart.yaml new file mode 100644 index 00000000000..e96b80c22d1 --- /dev/null +++ b/dts/bindings/serial/xtensa,esp32-uart.yaml @@ -0,0 +1,35 @@ +--- +title: ESP32 Uart +version: 0.1 + +description: > + This binding gives a base representation of the ESP32 UART + +inherits: + !include uart.yaml + +properties: + compatible: + type: string + category: required + description: compatible strings + constraint: "xtensa,esp32-uart" + + reg: + type: array + description: mmio register space + generation: define + category: required + + interrupts: + type: array + category: required + description: required interrupts + generation: define + + clocks: + type: array + category: required + description: Clock gate control information + generation: structures +... diff --git a/dts/xtensa/esp32.dtsi b/dts/xtensa/esp32.dtsi new file mode 100644 index 00000000000..548ac00781f --- /dev/null +++ b/dts/xtensa/esp32.dtsi @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2019 Intel Corporation. + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "skeleton.dtsi" + +/ { + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "LX6"; + reg = <0>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "LX6"; + reg = <1>; + }; + + }; + + sram0: memory@3ffb0000 { + device_type = "memory"; + compatible = "mmio-sram"; + reg = <0x3FFB0000 0x50000>; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges; + + uart0: uart@40008fd0 { + compatible = "xtensa,esp32-uart"; + reg = <0x40008fd0 0x400>; + label = "ROMUART"; + + status = "disabled"; + }; + + }; +}; diff --git a/soc/xtensa/esp32/linker.ld b/soc/xtensa/esp32/linker.ld index 7928e8c6559..405e0ac6bec 100644 --- a/soc/xtensa/esp32/linker.ld +++ b/soc/xtensa/esp32/linker.ld @@ -14,6 +14,7 @@ #define _LINKER #define _ASMLANGUAGE +#include #include #include #include