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arch/x86: refactor APIC timer configuration to SoC level

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The APIC is part of the SoC, not the board, so move the defaults down.

Signed-off-by: Charles E. Youse <charles.youse@intel.com>
This commit is contained in:
Charles E. Youse 2019-09-16 13:50:56 -04:00 • committed by Andrew Boie
commit 3bc79fdf2c
3 changed files with 22 additions and 23 deletions
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2
boards/x86/gpmrb/gpmrb_defconfig
View file

@ -4,7 +4,7 @@
CONFIG_X86=y
CONFIG_SOC_APOLLO_LAKE=y
CONFIG_BOARD_GPMRB=y
CONFIG_HPET_TIMER=y
CONFIG_APIC_TIMER=y
CONFIG_PIC_DISABLE=y
CONFIG_LOAPIC=y
CONFIG_CONSOLE=y

20
boards/x86/up_squared/Kconfig.defconfig
View file

@ -31,24 +31,4 @@ endif # I2C
config APIC_TIMER
default y if !HPET_TIMER
if APIC_TIMER
config APIC_TIMER_IRQ
default 24
config APIC_TIMER_TSC
default y
if APIC_TIMER_TSC
config APIC_TIMER_TSC_M
default 3
config APIC_TIMER_TSC_N
default 249
endif # APIC_TIMER_TSC
endif # APIC_TIMER
endif # BOARD_UP_SQUARED

23
soc/x86/apollo_lake/Kconfig.defconfig
View file

@ -13,8 +13,27 @@ config SOC
default "apollo_lake"
config SYS_CLOCK_HW_CYCLES_PER_SEC
default 150000000 if LOAPIC_TIMER
default 25000000 if HPET_TIMER
default 19200000
if APIC_TIMER
config APIC_TIMER_IRQ
default 24
config APIC_TIMER_TSC
default y
if APIC_TIMER_TSC
config APIC_TIMER_TSC_M
default 3
config APIC_TIMER_TSC_N
default 249
endif # APIC_TIMER_TSC
endif # APIC_TIMER
config CLFLUSH_DETECT
default y if CACHE_FLUSHING