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interrupt_controller: plic: use shared symbol for DT_*

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miv already had it defined, but let's shorten the names and use
them in the driver. This also adds it for sifive-freedom.

Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson 2020-01-04 09:56:42 -08:00 • committed by Anas Nashif
commit 3b733b5282
3 changed files with 21 additions and 24 deletions
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26
drivers/interrupt_controller/intc_plic.c
View file

@ -42,8 +42,7 @@ static int save_irq;
void riscv_plic_irq_enable(u32_t irq) void riscv_plic_irq_enable(u32_t irq)
{ {
u32_t key; u32_t key;
volatile u32_t *en = volatile u32_t *en = (volatile u32_t *)DT_PLIC_IRQ_EN;
(volatile u32_t *)DT_INST_0_SIFIVE_PLIC_1_0_0_IRQ_EN_BASE_ADDRESS;
key = irq_lock(); key = irq_lock();
en += (irq >> 5); en += (irq >> 5);
@ -66,8 +65,7 @@ void riscv_plic_irq_enable(u32_t irq)
void riscv_plic_irq_disable(u32_t irq) void riscv_plic_irq_disable(u32_t irq)
{ {
u32_t key; u32_t key;
volatile u32_t *en = volatile u32_t *en = (volatile u32_t *)DT_PLIC_IRQ_EN;
(volatile u32_t *)DT_INST_0_SIFIVE_PLIC_1_0_0_IRQ_EN_BASE_ADDRESS;
key = irq_lock(); key = irq_lock();
en += (irq >> 5); en += (irq >> 5);
@ -86,8 +84,7 @@ void riscv_plic_irq_disable(u32_t irq)
*/ */
int riscv_plic_irq_is_enabled(u32_t irq) int riscv_plic_irq_is_enabled(u32_t irq)
{ {
volatile u32_t *en = volatile u32_t *en = (volatile u32_t *)DT_PLIC_IRQ_EN;
(volatile u32_t *)DT_INST_0_SIFIVE_PLIC_1_0_0_IRQ_EN_BASE_ADDRESS;
en += (irq >> 5); en += (irq >> 5);
return !!(*en & (1 << (irq & 31))); return !!(*en & (1 << (irq & 31)));
@ -106,11 +103,10 @@ int riscv_plic_irq_is_enabled(u32_t irq)
*/ */
void riscv_plic_set_priority(u32_t irq, u32_t priority) void riscv_plic_set_priority(u32_t irq, u32_t priority)
{ {
volatile u32_t *prio = volatile u32_t *prio = (volatile u32_t *)DT_PLIC_PRIO;
(volatile u32_t *)DT_INST_0_SIFIVE_PLIC_1_0_0_PRIO_BASE_ADDRESS;
if (priority > DT_INST_0_SIFIVE_PLIC_1_0_0_RISCV_MAX_PRIORITY) if (priority > DT_PLIC_MAX_PRIO)
priority = DT_INST_0_SIFIVE_PLIC_1_0_0_RISCV_MAX_PRIORITY; priority = DT_PLIC_MAX_PRIO;
prio += irq; prio += irq;
*prio = priority; *prio = priority;
@ -134,7 +130,7 @@ int riscv_plic_get_irq(void)
static void plic_irq_handler(void *arg) static void plic_irq_handler(void *arg)
{ {
volatile struct plic_regs_t *regs = volatile struct plic_regs_t *regs =
(volatile struct plic_regs_t *) DT_INST_0_SIFIVE_PLIC_1_0_0_REG_BASE_ADDRESS; (volatile struct plic_regs_t *) DT_PLIC_REG;
u32_t irq; u32_t irq;
struct _isr_table_entry *ite; struct _isr_table_entry *ite;
@ -179,12 +175,10 @@ static int plic_init(struct device *dev)
{ {
ARG_UNUSED(dev); ARG_UNUSED(dev);
volatile u32_t *en = volatile u32_t *en = (volatile u32_t *)DT_PLIC_IRQ_EN;
(volatile u32_t *)DT_INST_0_SIFIVE_PLIC_1_0_0_IRQ_EN_BASE_ADDRESS; volatile u32_t *prio = (volatile u32_t *)DT_PLIC_PRIO;
volatile u32_t *prio =
(volatile u32_t *)DT_INST_0_SIFIVE_PLIC_1_0_0_PRIO_BASE_ADDRESS;
volatile struct plic_regs_t *regs = volatile struct plic_regs_t *regs =
(volatile struct plic_regs_t *)DT_INST_0_SIFIVE_PLIC_1_0_0_REG_BASE_ADDRESS; (volatile struct plic_regs_t *)DT_PLIC_REG;
int i; int i;
/* Ensure that all interrupts are disabled initially */ /* Ensure that all interrupts are disabled initially */

12
soc/riscv/riscv-privilege/miv/dts_fixup.h
View file

@ -2,14 +2,10 @@
/* PLIC */ /* PLIC */
#define DT_PLIC_MAX_PRIORITY \ #define DT_PLIC_MAX_PRIO DT_SIFIVE_PLIC_1_0_0_40000000_RISCV_MAX_PRIORITY
DT_SIFIVE_PLIC_1_0_0_40000000_RISCV_MAX_PRIORITY #define DT_PLIC_PRIO DT_SIFIVE_PLIC_1_0_0_40000000_PRIO_BASE_ADDRESS
#define DT_PLIC_PRIO_BASE_ADDR \ #define DT_PLIC_IRQ_EN DT_SIFIVE_PLIC_1_0_0_40000000_IRQ_EN_BASE_ADDRESS
DT_SIFIVE_PLIC_1_0_0_40000000_PRIO_BASE_ADDRESS #define DT_PLIC_REG DT_SIFIVE_PLIC_1_0_0_40000000_REG_BASE_ADDRESS
#define DT_PLIC_IRQ_EN_BASE_ADDR \
DT_SIFIVE_PLIC_1_0_0_40000000_IRQ_EN_BASE_ADDRESS
#define DT_PLIC_REG_BASE_ADDR \
DT_SIFIVE_PLIC_1_0_0_40000000_REG_BASE_ADDRESS
/* UART 0 */ /* UART 0 */
#define DT_MIV_UART_0_BASE_ADDR DT_MICROSEMI_COREUART_70001000_BASE_ADDRESS #define DT_MIV_UART_0_BASE_ADDR DT_MICROSEMI_COREUART_70001000_BASE_ADDRESS

7
soc/riscv/riscv-privilege/sifive-freedom/dts_fixup.h Normal file
View file

@ -0,0 +1,7 @@
/* SPDX-License-Identifier: Apache-2.0 */
/* Copyright (c) 2020 Olof Johansson <olof@lixom.net> */
#define DT_PLIC_MAX_PRIO DT_INST_0_SIFIVE_PLIC_1_0_0_RISCV_MAX_PRIORITY
#define DT_PLIC_PRIO DT_INST_0_SIFIVE_PLIC_1_0_0_PRIO_BASE_ADDRESS
#define DT_PLIC_IRQ_EN DT_INST_0_SIFIVE_PLIC_1_0_0_IRQ_EN_BASE_ADDRESS
#define DT_PLIC_REG DT_INST_0_SIFIVE_PLIC_1_0_0_REG_BASE_ADDRESS