drivers: serial: nrfx_uarte: add support for pinctrl
This patch adds support for the new pinctrl API to the UARTE driver. The old pin property based solution is still kept so that users have time to transition to the new model. Notes: - Some build assertions cannot be performed since the driver does not have direct access to pin settings anymore. As a result user will not be notified if HWFC is enabled but RTS/CTS pins are not configured. - Hardware flow control can be enabled regardless of pin configuration, it is now up to the user to configure RTS/CTS pins in DT. - Some RX enable checks that were performed using pin information has been replaced with a DT property that informs if RX is enabled or not. Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
This commit is contained in:
Gerard Marull-Paretas
Carles Cufí
parent
6399ad50f4
commit
3b7215e160
2 changed files with 208 additions and 164 deletions
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@ -9,7 +9,7 @@
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*/
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#include <drivers/uart.h>
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#include <hal/nrf_gpio.h>
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#include <hal/nrf_uarte.h>
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#include <nrfx_timer.h>
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#include <sys/util.h>
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@ -18,6 +18,12 @@
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#include <helpers/nrfx_gppi.h>
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LOG_MODULE_REGISTER(uart_nrfx_uarte, LOG_LEVEL_ERR);
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#ifdef CONFIG_PINCTRL
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#include <drivers/pinctrl.h>
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#else
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#include <hal/nrf_gpio.h>
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#endif /* CONFIG_PINCTRL */
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/* Generalize PPI or DPPI channel management */
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#if defined(CONFIG_HAS_HW_NRF_PPI)
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#include <nrfx_ppi.h>
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@ -132,41 +138,34 @@ struct uarte_nrfx_data {
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#define UARTE_LOW_POWER_TX BIT(0)
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#define UARTE_LOW_POWER_RX BIT(1)
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/* Flag indicating that CTS pin is used. */
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#define UARTE_CFG_FLAG_CTS_PIN_SET BIT(0)
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/* Flag indicating that RTS pin is used. */
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#define UARTE_CFG_FLAG_RTS_PIN_SET BIT(1)
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/* If enabled, pins are managed when going to low power mode. */
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#define UARTE_CFG_FLAG_GPIO_MGMT BIT(2)
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#define UARTE_CFG_FLAG_GPIO_MGMT BIT(0)
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/* If enabled then ENDTX is PPI'ed to TXSTOP */
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#define UARTE_CFG_FLAG_PPI_ENDTX BIT(3)
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#define UARTE_CFG_FLAG_PPI_ENDTX BIT(1)
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/* If enabled then UARTE peripheral is disabled when not used. This allows
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* to achieve lowest power consumption in idle.
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*/
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#define UARTE_CFG_FLAG_LOW_POWER BIT(4)
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#define IS_CTS_PIN_SET(flags) (flags & UARTE_CFG_FLAG_CTS_PIN_SET)
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#define IS_RTS_PIN_SET(flags) (flags & UARTE_CFG_FLAG_RTS_PIN_SET)
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#define IS_HWFC_PINS_USED(flags) \
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(IS_CTS_PIN_SET(flags) | IS_RTS_PIN_SET(flags))
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/**
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* @brief Structure for UARTE configuration.
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*/
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struct uarte_nrfx_config {
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NRF_UARTE_Type *uarte_regs; /* Instance address */
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uint32_t flags;
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uint32_t pseltxd; /* PSEL.TXD register value */
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uint32_t pselrxd; /* PSEL.RXD register value */
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uint32_t pselcts; /* PSEL.CTS register value */
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uint32_t pselrts; /* PSEL.RTS register value */
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nrf_gpio_pin_pull_t rxd_pull; /* RXD pin pull configuration */
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nrf_gpio_pin_pull_t cts_pull; /* CTS pin pull configuration */
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bool disable_rx;
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#ifdef CONFIG_PINCTRL
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const struct pinctrl_dev_config *pcfg;
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#else
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uint32_t tx_pin;
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uint32_t rx_pin;
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uint32_t rts_pin;
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uint32_t cts_pin;
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bool rx_pull_up;
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bool cts_pull_up;
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#endif /* CONFIG_PINCTRL */
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#ifdef CONFIG_UART_ASYNC_API
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nrfx_timer_t timer;
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#endif
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@ -189,6 +188,58 @@ static inline NRF_UARTE_Type *get_uarte_instance(const struct device *dev)
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return config->uarte_regs;
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}
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#ifndef CONFIG_PINCTRL
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static void uarte_nrfx_pins_configure(const struct device *dev, bool sleep)
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{
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const struct uarte_nrfx_config *cfg = get_dev_config(dev);
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if (!sleep) {
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if (cfg->tx_pin != NRF_UARTE_PSEL_DISCONNECTED) {
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nrf_gpio_pin_write(cfg->tx_pin, 1);
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nrf_gpio_cfg_output(cfg->tx_pin);
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}
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if (cfg->rx_pin != NRF_UARTE_PSEL_DISCONNECTED) {
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nrf_gpio_cfg_input(cfg->rx_pin,
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(cfg->rx_pull_up ?
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NRF_GPIO_PIN_PULLUP :
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NRF_GPIO_PIN_NOPULL));
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}
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if (cfg->rts_pin != NRF_UARTE_PSEL_DISCONNECTED) {
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nrf_gpio_pin_write(cfg->rts_pin, 1);
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nrf_gpio_cfg_output(cfg->rts_pin);
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}
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if (cfg->cts_pin != NRF_UARTE_PSEL_DISCONNECTED) {
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nrf_gpio_cfg_input(cfg->cts_pin,
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(cfg->cts_pull_up ?
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NRF_GPIO_PIN_PULLUP :
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NRF_GPIO_PIN_NOPULL));
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}
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} else {
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if (cfg->tx_pin != NRF_UARTE_PSEL_DISCONNECTED) {
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nrf_gpio_cfg_default(cfg->tx_pin);
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}
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if (cfg->rx_pin != NRF_UARTE_PSEL_DISCONNECTED) {
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nrf_gpio_cfg_default(cfg->rx_pin);
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}
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if (cfg->rts_pin != NRF_UARTE_PSEL_DISCONNECTED) {
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nrf_gpio_cfg_default(cfg->rts_pin);
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}
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if (cfg->cts_pin != NRF_UARTE_PSEL_DISCONNECTED) {
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nrf_gpio_cfg_default(cfg->cts_pin);
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}
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}
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nrf_uarte_txrx_pins_set(cfg->uarte_regs, cfg->tx_pin, cfg->rx_pin);
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nrf_uarte_hwfc_pins_set(cfg->uarte_regs, cfg->rts_pin, cfg->cts_pin);
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}
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#endif /* !CONFIG_PINCTRL */
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static void endtx_isr(const struct device *dev)
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{
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NRF_UARTE_Type *uarte = get_uarte_instance(dev);
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@ -395,11 +446,7 @@ static int uarte_nrfx_configure(const struct device *dev,
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uarte_cfg.hwfc = NRF_UARTE_HWFC_DISABLED;
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break;
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case UART_CFG_FLOW_CTRL_RTS_CTS:
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if (IS_HWFC_PINS_USED(get_dev_config(dev)->flags)) {
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uarte_cfg.hwfc = NRF_UARTE_HWFC_ENABLED;
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} else {
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return -ENOTSUP;
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}
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break;
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default:
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return -ENOTSUP;
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@ -798,9 +845,10 @@ static int uarte_nrfx_rx_enable(const struct device *dev, uint8_t *buf,
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int32_t timeout)
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{
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struct uarte_nrfx_data *data = get_dev_data(dev);
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const struct uarte_nrfx_config *cfg = get_dev_config(dev);
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NRF_UARTE_Type *uarte = get_uarte_instance(dev);
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if (nrf_uarte_rx_pin_get(uarte) == NRF_UARTE_PSEL_DISCONNECTED) {
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if (cfg->disable_rx) {
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__ASSERT(false, "TX only UARTE instance");
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return -ENOTSUP;
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}
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@ -1680,25 +1728,14 @@ static int uarte_instance_init(const struct device *dev,
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data->dev = dev;
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nrf_gpio_pin_write(cfg->pseltxd, 1);
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nrf_gpio_cfg_output(cfg->pseltxd);
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if (cfg->pselrxd != NRF_UARTE_PSEL_DISCONNECTED) {
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nrf_gpio_cfg_input(cfg->pselrxd, cfg->rxd_pull);
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#ifdef CONFIG_PINCTRL
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err = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT);
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if (err < 0) {
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return err;
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}
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nrf_uarte_txrx_pins_set(uarte, cfg->pseltxd, cfg->pselrxd);
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if (cfg->pselcts != NRF_UARTE_PSEL_DISCONNECTED) {
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nrf_gpio_cfg_input(cfg->pselcts, cfg->cts_pull);
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}
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if (cfg->pselrts != NRF_UARTE_PSEL_DISCONNECTED) {
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nrf_gpio_pin_write(cfg->pselrts, 1);
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nrf_gpio_cfg_output(cfg->pselrts);
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}
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nrf_uarte_hwfc_pins_set(uarte, cfg->pselrts, cfg->pselcts);
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#else
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uarte_nrfx_pins_configure(dev, false);
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#endif /* CONFIG_PINCTRL */
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err = uarte_nrfx_configure(dev, &get_dev_data(dev)->uart_config);
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if (err) {
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@ -1726,7 +1763,7 @@ static int uarte_instance_init(const struct device *dev,
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/* Enable receiver and transmitter */
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nrf_uarte_enable(uarte);
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if (cfg->pselrxd != NRF_UARTE_PSEL_DISCONNECTED) {
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if (!cfg->disable_rx) {
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nrf_uarte_event_clear(uarte, NRF_UARTE_EVENT_ENDRX);
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nrf_uarte_rx_buffer_set(uarte, &data->rx_data, 1);
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@ -1756,46 +1793,6 @@ static int uarte_instance_init(const struct device *dev,
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}
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#ifdef CONFIG_PM_DEVICE
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static void uarte_nrfx_pins_enable(const struct device *dev, bool enable)
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{
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const struct uarte_nrfx_config *cfg = get_dev_config(dev);
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if (!(cfg->flags & UARTE_CFG_FLAG_GPIO_MGMT)) {
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return;
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}
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if (enable) {
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nrf_gpio_pin_write(cfg->pseltxd, 1);
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nrf_gpio_cfg_output(cfg->pseltxd);
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if (cfg->pselrxd != NRF_UARTE_PSEL_DISCONNECTED) {
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nrf_gpio_cfg_input(cfg->pselrxd, cfg->rxd_pull);
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}
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if (IS_RTS_PIN_SET(cfg->flags)) {
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nrf_gpio_pin_write(cfg->pselrts, 1);
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nrf_gpio_cfg_output(cfg->pselrts);
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}
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if (IS_CTS_PIN_SET(cfg->flags)) {
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nrf_gpio_cfg_input(cfg->pselcts, cfg->cts_pull);
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}
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} else {
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nrf_gpio_cfg_default(cfg->pseltxd);
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if (cfg->pselrxd != NRF_UARTE_PSEL_DISCONNECTED) {
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nrf_gpio_cfg_default(cfg->pselrxd);
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}
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if (IS_RTS_PIN_SET(cfg->flags)) {
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nrf_gpio_cfg_default(cfg->pselrts);
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}
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if (IS_CTS_PIN_SET(cfg->flags)) {
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nrf_gpio_cfg_default(cfg->pselcts);
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}
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}
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}
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/** @brief Pend until TX is stopped.
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*
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* There are 2 configurations that must be handled:
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@ -1838,10 +1835,25 @@ static int uarte_nrfx_pm_action(const struct device *dev,
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#if defined(CONFIG_UART_ASYNC_API) || defined(UARTE_INTERRUPT_DRIVEN)
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struct uarte_nrfx_data *data = get_dev_data(dev);
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#endif
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const struct uarte_nrfx_config *cfg = get_dev_config(dev);
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#ifdef CONFIG_PINCTRL
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int ret;
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#endif
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switch (action) {
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case PM_DEVICE_ACTION_RESUME:
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uarte_nrfx_pins_enable(dev, true);
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if (cfg->flags & UARTE_CFG_FLAG_GPIO_MGMT) {
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#ifdef CONFIG_PINCTRL
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ret = pinctrl_apply_state(cfg->pcfg,
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PINCTRL_STATE_DEFAULT);
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if (ret < 0) {
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return ret;
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}
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#else
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uarte_nrfx_pins_configure(dev, false);
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#endif /* CONFIG_PINCTRL */
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}
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nrf_uarte_enable(uarte);
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#ifdef CONFIG_UART_ASYNC_API
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@ -1852,7 +1864,7 @@ static int uarte_nrfx_pm_action(const struct device *dev,
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return 0;
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}
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#endif
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if (nrf_uarte_rx_pin_get(uarte) != NRF_UARTE_PSEL_DISCONNECTED) {
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if (!cfg->disable_rx) {
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nrf_uarte_event_clear(uarte, NRF_UARTE_EVENT_ENDRX);
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nrf_uarte_task_trigger(uarte, NRF_UARTE_TASK_STARTRX);
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@ -1905,7 +1917,19 @@ static int uarte_nrfx_pm_action(const struct device *dev,
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wait_for_tx_stopped(dev);
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uart_disable(dev);
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uarte_nrfx_pins_enable(dev, false);
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if (cfg->flags & UARTE_CFG_FLAG_GPIO_MGMT) {
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#ifdef CONFIG_PINCTRL
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ret = pinctrl_apply_state(cfg->pcfg,
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PINCTRL_STATE_SLEEP);
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if (ret < 0) {
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return ret;
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}
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#else
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uarte_nrfx_pins_configure(dev, true);
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#endif /* CONFIG_PINCTRL */
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}
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break;
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default:
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return -ENOTSUP;
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@ -1919,19 +1943,6 @@ static int uarte_nrfx_pm_action(const struct device *dev,
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#define UARTE_HAS_PROP(idx, prop) DT_NODE_HAS_PROP(UARTE(idx), prop)
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#define UARTE_PROP(idx, prop) DT_PROP(UARTE(idx), prop)
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#define UARTE_PSEL(idx, pin_prop) \
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COND_CODE_1(UARTE_HAS_PROP(idx, pin_prop), \
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(UARTE_PROP(idx, pin_prop)), \
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(NRF_UARTE_PSEL_DISCONNECTED))
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#define UARTE_PULL(idx, pull_up_prop) \
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COND_CODE_1(UARTE_PROP(idx, pull_up_prop), \
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(NRF_GPIO_PIN_PULLUP), \
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(NRF_GPIO_PIN_NOPULL))
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#define HWFC_AVAILABLE(idx) \
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(UARTE_HAS_PROP(idx, rts_pin) || UARTE_HAS_PROP(idx, cts_pin))
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#define UARTE_IRQ_CONFIGURE(idx, isr_handler) \
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do { \
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IRQ_CONNECT(DT_IRQN(UARTE(idx)), DT_IRQ(UARTE(idx), priority), \
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@ -1939,13 +1950,19 @@ static int uarte_nrfx_pm_action(const struct device *dev,
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irq_enable(DT_IRQN(UARTE(idx))); \
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} while (0)
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#define HWFC_CONFIG_CHECK(idx) \
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BUILD_ASSERT( \
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(UARTE_PROP(idx, hw_flow_control) && HWFC_AVAILABLE(idx)) \
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|| \
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!UARTE_PROP(idx, hw_flow_control) \
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)
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#ifdef CONFIG_PINCTRL
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/* Low power mode is used when disable_rx is not defined or in async mode if
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* kconfig option is enabled.
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*/
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#define USE_LOW_POWER(idx) \
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((!UARTE_HAS_PROP(idx, disable_rx) && \
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COND_CODE_1(CONFIG_UART_##idx##_ASYNC, \
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(!IS_ENABLED(CONFIG_UART_##idx##_NRF_ASYNC_LOW_POWER)), \
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(1))) ? 0 : UARTE_CFG_FLAG_LOW_POWER)
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#define UARTE_DISABLE_RX_INIT(node_id) \
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.disable_rx = DT_PROP(node_id, disable_rx)
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#else
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/* Low power mode is used when rx pin is not defined or in async mode if
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* kconfig option is enabled.
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*/
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@ -1955,10 +1972,14 @@ static int uarte_nrfx_pm_action(const struct device *dev,
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(!IS_ENABLED(CONFIG_UART_##idx##_NRF_ASYNC_LOW_POWER)), \
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(1))) ? 0 : UARTE_CFG_FLAG_LOW_POWER)
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#define UARTE_DISABLE_RX_INIT(node_id) \
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.disable_rx = DT_NODE_HAS_PROP(node_id, rx_pin) ? false : true
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#endif /* CONFIG_PINCTRL */
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#define UART_NRF_UARTE_DEVICE(idx) \
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HWFC_CONFIG_CHECK(idx); \
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UARTE_INT_DRIVEN(idx); \
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UARTE_ASYNC(idx); \
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IF_ENABLED(CONFIG_PINCTRL, (PINCTRL_DT_DEFINE(UARTE(idx)))) \
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static struct uarte_nrfx_data uarte_##idx##_data = { \
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UARTE_CONFIG(idx), \
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IF_ENABLED(CONFIG_UART_##idx##_ASYNC, \
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@ -1967,23 +1988,26 @@ static int uarte_nrfx_pm_action(const struct device *dev,
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(.int_driven = &uarte##idx##_int_driven,)) \
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}; \
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static const struct uarte_nrfx_config uarte_##idx##z_config = { \
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COND_CODE_1(CONFIG_PINCTRL, \
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(.pcfg = PINCTRL_DT_DEV_CONFIG_GET(UARTE(idx)),), \
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(.tx_pin = DT_PROP_OR(UARTE(idx), tx_pin, \
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NRF_UARTE_PSEL_DISCONNECTED), \
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.rx_pin = DT_PROP_OR(UARTE(idx), rx_pin, \
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NRF_UARTE_PSEL_DISCONNECTED), \
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.rts_pin = DT_PROP_OR(UARTE(idx), rts_pin, \
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NRF_UARTE_PSEL_DISCONNECTED), \
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.cts_pin = DT_PROP_OR(UARTE(idx), cts_pin, \
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NRF_UARTE_PSEL_DISCONNECTED), \
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.rx_pull_up = DT_PROP(UARTE(idx), rx_pull_up), \
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.cts_pull_up = DT_PROP(UARTE(idx), cts_pull_up),)) \
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.uarte_regs = (NRF_UARTE_Type *)DT_REG_ADDR(UARTE(idx)), \
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.flags = \
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(UARTE_HAS_PROP(idx, rts_pin) ? \
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UARTE_CFG_FLAG_RTS_PIN_SET : 0) | \
|
||||
(UARTE_HAS_PROP(idx, cts_pin) ? \
|
||||
UARTE_CFG_FLAG_CTS_PIN_SET : 0) | \
|
||||
(IS_ENABLED(CONFIG_UART_##idx##_GPIO_MANAGEMENT) ? \
|
||||
UARTE_CFG_FLAG_GPIO_MGMT : 0) | \
|
||||
(IS_ENABLED(CONFIG_UART_##idx##_ENHANCED_POLL_OUT) ? \
|
||||
UARTE_CFG_FLAG_PPI_ENDTX : 0) | \
|
||||
USE_LOW_POWER(idx), \
|
||||
.pseltxd = UARTE_PROP(idx, tx_pin), /* must be set */ \
|
||||
.pselrxd = UARTE_PSEL(idx, rx_pin), /* optional */ \
|
||||
.pselcts = UARTE_PSEL(idx, cts_pin), /* optional */ \
|
||||
.pselrts = UARTE_PSEL(idx, rts_pin), /* optional */ \
|
||||
.rxd_pull = UARTE_PULL(idx, rx_pull_up), \
|
||||
.cts_pull = UARTE_PULL(idx, cts_pull_up), \
|
||||
UARTE_DISABLE_RX_INIT(UARTE(idx)), \
|
||||
IF_ENABLED(CONFIG_UART_##idx##_NRF_HW_ASYNC, \
|
||||
(.timer = NRFX_TIMER_INSTANCE( \
|
||||
CONFIG_UART_##idx##_NRF_HW_ASYNC_TIMER),)) \
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
include: uart-controller.yaml
|
||||
include: [uart-controller.yaml, pinctrl-device.yaml]
|
||||
|
||||
properties:
|
||||
reg:
|
||||
|
|
@ -7,42 +7,11 @@ properties:
|
|||
interrupts:
|
||||
required: true
|
||||
|
||||
tx-pin:
|
||||
type: int
|
||||
required: true
|
||||
disable-rx:
|
||||
type: boolean
|
||||
description: |
|
||||
The TX pin to use.
|
||||
|
||||
For pins P0.0 through P0.31, use the pin number. For example,
|
||||
to use P0.16 for TX, set:
|
||||
|
||||
tx-pin = <16>;
|
||||
|
||||
For pins P1.0 through P1.31, add 32 to the pin number. For
|
||||
example, to use P1.2 for TX, set:
|
||||
|
||||
tx-pin = <34>; /* 32 + 2 */
|
||||
|
||||
rx-pin:
|
||||
type: int
|
||||
required: false
|
||||
description: |
|
||||
The RX pin to use. The pin numbering scheme is the same as the
|
||||
tx-pin property's.
|
||||
|
||||
rts-pin:
|
||||
type: int
|
||||
required: false
|
||||
description: |
|
||||
The RTS pin to use. The pin numbering scheme is the same as the
|
||||
tx-pin property's.
|
||||
|
||||
cts-pin:
|
||||
type: int
|
||||
required: false
|
||||
description: |
|
||||
The CTS pin to use. The pin numbering scheme is the same as the
|
||||
tx-pin property's.
|
||||
Disable UART reception capabilities (only required to disable reception
|
||||
if CONFIG_PINCTRL is enabled).
|
||||
|
||||
current-speed:
|
||||
description: |
|
||||
|
|
@ -68,12 +37,63 @@ properties:
|
|||
- 921600
|
||||
- 1000000
|
||||
|
||||
tx-pin:
|
||||
type: int
|
||||
description: |
|
||||
IMPORTANT: This option will only be used if the new pin control driver
|
||||
is not enabled. It will be deprecated in the future.
|
||||
|
||||
The TX pin to use.
|
||||
|
||||
For pins P0.0 through P0.31, use the pin number. For example,
|
||||
to use P0.16 for TX, set:
|
||||
|
||||
tx-pin = <16>;
|
||||
|
||||
For pins P1.0 through P1.31, add 32 to the pin number. For
|
||||
example, to use P1.2 for TX, set:
|
||||
|
||||
tx-pin = <34>; /* 32 + 2 */
|
||||
|
||||
rx-pin:
|
||||
type: int
|
||||
description: |
|
||||
IMPORTANT: This option will only be used if the new pin control driver
|
||||
is not enabled. It will be deprecated in the future.
|
||||
|
||||
The RX pin to use. The pin numbering scheme is the same as the
|
||||
tx-pin property's.
|
||||
|
||||
rts-pin:
|
||||
type: int
|
||||
description: |
|
||||
IMPORTANT: This option will only be used if the new pin control driver
|
||||
is not enabled. It will be deprecated in the future.
|
||||
|
||||
The RTS pin to use. The pin numbering scheme is the same as the
|
||||
tx-pin property's.
|
||||
|
||||
cts-pin:
|
||||
type: int
|
||||
description: |
|
||||
IMPORTANT: This option will only be used if the new pin control driver
|
||||
is not enabled. It will be deprecated in the future.
|
||||
|
||||
The CTS pin to use. The pin numbering scheme is the same as the
|
||||
tx-pin property's.
|
||||
|
||||
rx-pull-up:
|
||||
type: boolean
|
||||
required: false
|
||||
description: Enable pull-up resistor on the RX pin.
|
||||
description: |
|
||||
IMPORTANT: This option will only be used if the new pin control driver
|
||||
is not enabled. It will be deprecated in the future.
|
||||
|
||||
Enable pull-up resistor on the RX pin.
|
||||
|
||||
cts-pull-up:
|
||||
type: boolean
|
||||
required: false
|
||||
description: Enable pull-up resistor on the CTS pin.
|
||||
description: |
|
||||
IMPORTANT: This option will only be used if the new pin control driver
|
||||
is not enabled. It will be deprecated in the future.
|
||||
|
||||
Enable pull-up resistor on the CTS pin.
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue