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arm: work around QEMU issue with _IsInIsr

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The ICSR RETTOBASE bit is improperly implemented in QEMU (the polarity
is flipped) and the fix for it has not yet made it into a QEMU release,
although it is present in upstream master branch.

The symptom is that if we are not in thread mode, the system always
believes were are in a nested exception state, causing _IsInIsr() to
always return true.

Skip the nested exception check if we are building for QEMU.

This is a workaround until SDK-54 is resolved.

Issue: SDK-54
Change-Id: I06eafcc85fb76a9b23b4ba85ed6e111a08516231
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
This commit is contained in:
Andrew Boie 2017-04-19 15:23:51 -07:00 • committed by Anas Nashif
commit 3b662555d1
1 changed files with 19 additions and 9 deletions
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28
arch/arm/include/cortex_m/exc.h
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@ -44,20 +44,30 @@ static ALWAYS_INLINE int _IsInIsr(void)
{
u32_t vector = _IpsrGet();
/*
* IRQs + PendSV (14) + SVC (11) + SYSTICK (15) are interrupts.
* Vectors 12 and 13 are reserved, we'll never be in there
* On ARMv6-M there is no nested execution bit, so we check exception 3,
* hard fault, to a detect a nested exception.
*/
/* IRQs + PendSV (14) + SVC (11) + SYSTICK (15) are interrupts. */
return (vector > 10)
#if defined(CONFIG_ARMV6_M)
return (vector > 10) || (vector == 3);
/* On ARMv6-M there is no nested execution bit, so we check
* exception 3, hard fault, to a detect a nested exception.
*/
|| (vector == 3)
#elif defined(CONFIG_ARMV7_M)
return (vector > 10) ||
(vector && !(SCB->ICSR & SCB_ICSR_RETTOBASE_Msk));
/* If not in thread mode, and if RETTOBASE bit in ICSR is 0,
* then there are preempted active exceptions to execute.
*/
#ifndef CONFIG_BOARD_QEMU_CORTEX_M3
/* The polarity of RETTOBASE is incorrectly flipped in
* all but the very latest master tip of QEMU's NVIC driver,
* see commit "armv7m: Rewrite NVIC to not use any GIC code".
* Until QEMU 2.9 is released, and the SDK is updated to
* include it, skip this check in QEMU.
*/
|| (vector && !(SCB->ICSR & SCB_ICSR_RETTOBASE_Msk))
#endif /* CONFIG_BOARD_QEMU_CORTEX_M3 */
#else
#error Unknown ARM architecture
#endif /* CONFIG_ARMV6_M */
;
}
#define _EXC_SVC_PRIO 0