soc: arm: nxp_lpc: convert NXP LPC SOCs to use CMSIS SystemInit

Convert NXP LPC SOCs to use CMSIS SystemInit, and remove redundant code
where it exists. This will enable initialization flows to be more
standardized across all platforms.

Since LPC54xxx and LPC55xxx series enables SRAM banks in SystemInit,
provide Kconfigs to bypass this setting and keep additional SRAM
banks unclocked.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>

soc/arm/nxp_imx/rt5xx/Kconfig.soc

@@ -103,4 +103,11 @@ config IMAGE_VECTOR_TABLE_OFFSET
 
 endif # NXP_IMX_RT5XX_BOOT_HEADER
 
+config IMXRT5XX_ENABLE_CODE_CACHE
+	bool "Enable code cache"
+	default y
+	help
+	  Enable code cache for FlexSPI region at boot. If this Kconfig is
+	  cleared, the CACHE64 controller will be disabled during SOC init
+
 endif # SOC_SERIES_IMX_RT5XX

soc/arm/nxp_imx/rt5xx/soc.c

@@ -20,6 +20,7 @@
 #include <soc.h>
 #include "fsl_power.h"
 #include "fsl_clock.h"
+#include <fsl_cache.h>
 
 #ifdef CONFIG_FLASH_MCUX_FLEXSPI_XIP
 #include "flash_clock_setup.h"
@@ -374,6 +375,10 @@ static int nxp_rt500_init(const struct device *arg)
 	 */
 	NMI_INIT();
 
+#ifndef CONFIG_IMXRT5XX_ENABLE_CODE_CACHE
+	CACHE64_DisableCache(CACHE64_CTRL0);
+#endif
+
 	/* restore interrupt state */
 	irq_unlock(oldLevel);
 

soc/arm/nxp_imx/rt6xx/Kconfig.soc

@@ -109,4 +109,11 @@ config IMAGE_VECTOR_TABLE_OFFSET
 
 endif # NXP_IMX_RT6XX_BOOT_HEADER
 
+config IMXRT6XX_ENABLE_CODE_CACHE
+	bool "Enable code cache"
+	default y
+	help
+	  Enable code cache for FlexSPI region at boot. If this Kconfig is
+	  cleared, the CACHE64 controller will be disabled during SOC init
+
 endif # SOC_SERIES_IMX_RT6XX

soc/arm/nxp_imx/rt6xx/soc.c

@@ -24,6 +24,7 @@
 #include <fsl_clock.h>
 #include <fsl_common.h>
 #include <fsl_device_registers.h>
+#include <fsl_cache.h>
 
 #ifdef CONFIG_FLASH_MCUX_FLEXSPI_XIP
 #include "flash_clock_setup.h"
@@ -385,6 +386,10 @@ static int nxp_rt600_init(const struct device *arg)
 	 */
 	NMI_INIT();
 
+#ifndef CONFIG_IMXRT6XX_ENABLE_CODE_CACHE
+	CACHE64_DisableCache(CACHE64);
+#endif
+
 	/* restore interrupt state */
 	irq_unlock(oldLevel);
 

soc/arm/nxp_lpc/lpc51u68/Kconfig.series

@@ -13,5 +13,6 @@ config SOC_SERIES_LPC51U68
 	select HAS_MCUX_SCTIMER
 	select SOC_FAMILY_LPC
 	select CPU_CORTEX_M_HAS_SYSTICK
+	select PLATFORM_SPECIFIC_INIT
 	help
 	  Enable support for LPC LPC51U68 MCU Series

soc/arm/nxp_lpc/lpc51u68/linker.ld

@@ -4,4 +4,9 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
+ /* The SDK CMIS SystemInit function sets VTOR equal to &__Vectors,
+  * so we create an alias for the symbol to Zephyr's vector table
+  */
+ __Vectors = _vector_table;
+
 #include <zephyr/arch/arm/aarch32/cortex_m/scripts/linker.ld>

soc/arm/nxp_lpc/lpc51u68/soc.c

@@ -52,4 +52,13 @@ int soc_init(const struct device *arg)
 	return 0;
 }
 
+#ifdef CONFIG_PLATFORM_SPECIFIC_INIT
+
+void z_arm_platform_init(void)
+{
+	SystemInit();
+}
+
+#endif /* CONFIG_PLATFORM_SPECIFIC_INIT */
+
 SYS_INIT(soc_init, PRE_KERNEL_1, 0);

soc/arm/nxp_lpc/lpc54xxx/CMakeLists.txt

@@ -12,3 +12,10 @@ zephyr_library_include_directories(
   ${ZEPHYR_BASE}/kernel/include
   ${ZEPHYR_BASE}/arch/${ARCH}/include
   )
+
+
+# CMSIS SystemInit allows us to skip enabling clock to SRAM2 bank via
+# this compiler definition
+if(NOT DEFINED CONFIG_LPC54XXX_SRAM2_CLOCK)
+zephyr_compile_definitions(DONT_ENABLE_DISABLED_RAMBANKS=1)
+endif()

soc/arm/nxp_lpc/lpc54xxx/Kconfig.series

@@ -11,5 +11,6 @@ config SOC_SERIES_LPC54XXX
 	select HAS_MCUX_SYSCON
 	select SOC_FAMILY_LPC
 	select CPU_CORTEX_M_HAS_SYSTICK
+	select PLATFORM_SPECIFIC_INIT
 	help
 	  Enable support for LPC LPC54XXX MCU series

soc/arm/nxp_lpc/lpc54xxx/Kconfig.soc

@@ -66,4 +66,12 @@ config BUILD_OUTPUT_INFO_HEADER
 	default y
 	depends on SECOND_CORE_MCUX && SOC_LPC54114_M0
 
+config LPC54XXX_SRAM2_CLOCK
+	bool "Clock LPC54XXX SRAM2"
+	default y
+	help
+	  SRAM2 ram bank is disabled out of reset. By default, CMSIS SystemInit
+	  will enable the clock to this RAM bank. Disable this Kconfig to leave
+	  this ram bank untouched out of reset.
+
 endif # SOC_SERIES_LPC54XXX

soc/arm/nxp_lpc/lpc54xxx/gcc/startup_LPC54114_cm4.S

@@ -40,6 +40,9 @@ shared_boot_entry:
     /* Flag for slave core (0) */
     movs    r4, 0
     movs    r5, 1
+    push {lr}
+    bl SystemInit
+    pop {lr}
 
     /* Determine which core (M0+ or M4) this code is running on */
     /* r2 = (((*cpu_id) >> 4) & 0xFFF); (M4 core == 0xC24) */

soc/arm/nxp_lpc/lpc54xxx/linker.ld

@@ -11,5 +11,9 @@
  * This is the linker script for both standard images and XIP images.
  */
 
+ /* The SDK CMIS SystemInit function sets VTOR equal to &__Vectors,
+  * so we create an alias for the symbol to Zephyr's vector table
+  */
+ __Vectors = _vector_table;
 
 #include <zephyr/arch/arm/aarch32/cortex_m/scripts/linker.ld>

soc/arm/nxp_lpc/lpc54xxx/soc.c

@@ -139,6 +139,18 @@ static int nxp_lpc54114_init(const struct device *arg)
 
 SYS_INIT(nxp_lpc54114_init, PRE_KERNEL_1, 0);
 
+#if defined(CONFIG_PLATFORM_SPECIFIC_INIT) && defined(CONFIG_SOC_LPC54114_M0)
+
+/* M4 core has a custom platform initialization routine in assembly,
+ * but M0 core does not. install one here to call SystemInit.
+ */
+void z_arm_platform_init(void)
+{
+	SystemInit();
+}
+
+#endif /* CONFIG_PLATFORM_SPECIFIC_INIT */
+
 
 #if defined(CONFIG_SECOND_CORE_MCUX) && defined(CONFIG_SOC_LPC54114_M4)
 

soc/arm/nxp_lpc/lpc55xxx/CMakeLists.txt

@@ -16,3 +16,9 @@ zephyr_linker_sources_ifdef(CONFIG_USB_DEVICE_DRIVER
   SECTIONS usb.ld)
 
 zephyr_compile_definitions_ifdef(CONFIG_USB_DEVICE_DRIVER USB_STACK_USE_DEDICATED_RAM=1)
+
+# CMSIS SystemInit allows us to skip enabling clock to SRAM banks via
+# this compiler definition
+if(NOT DEFINED CONFIG_LPC55XXX_SRAM_CLOCKS)
+zephyr_compile_definitions(DONT_ENABLE_DISABLED_RAMBANKS=1)
+endif()

soc/arm/nxp_lpc/lpc55xxx/Kconfig.series

@@ -13,5 +13,6 @@ config SOC_SERIES_LPC55XXX
 	select SOC_FAMILY_LPC
 	select CPU_CORTEX_M_HAS_SYSTICK
 	select CPU_CORTEX_M_HAS_DWT
+	select PLATFORM_SPECIFIC_INIT
 	help
 	  Enable support for LPC5500 Series MCU series

soc/arm/nxp_lpc/lpc55xxx/Kconfig.soc

@@ -139,4 +139,12 @@ config BUILD_OUTPUT_ADJUST_LMA
 	depends on SECOND_CORE_MCUX && SOC_LPC55S69_CPU1
 	default "0x10000000"
 
+config LPC55XXX_SRAM_CLOCKS
+	bool "CLock LPC SRAM banks"
+	default y
+	help
+	  SRAM controllers 1,2,3, and 4 are disabled at reset.
+	  By default, CMSIS SystemInit will enable the clock to these RAM banks.
+	  Disable this Kconfig to leave the ram banks untouched out of reset.
+
 endif # SOC_SERIES_LPC55XXX

soc/arm/nxp_lpc/lpc55xxx/linker.ld

@@ -11,5 +11,10 @@
  * This is the linker script for both standard images and XIP images.
  */
 
+ /* The SDK CMIS SystemInit function sets VTOR equal to &__Vectors,
+  * so we create an alias for the symbol to Zephyr's vector table
+  */
+ __Vectors = _vector_table;
+
 
 #include <zephyr/arch/arm/aarch32/cortex_m/scripts/linker.ld>

soc/arm/nxp_lpc/lpc55xxx/soc.c

@@ -264,6 +264,24 @@ static int nxp_lpc55xxx_init(const struct device *arg)
 	return 0;
 }
 
+#ifdef CONFIG_PLATFORM_SPECIFIC_INIT
+
+void z_arm_platform_init(void)
+{
+	SystemInit();
+
+
+#ifndef CONFIG_LOG_BACKEND_SWO
+	/*
+	 * SystemInit unconditionally enables the trace clock.
+	 * Disable the trace clock unless SWO is used
+	 */
+	 SYSCON->TRACECLKDIV = 0x4000000;
+#endif
+}
+
+#endif /* CONFIG_PLATFORM_SPECIFIC_INIT */
+
 SYS_INIT(nxp_lpc55xxx_init, PRE_KERNEL_1, 0);
 
 #if defined(CONFIG_SECOND_CORE_MCUX) && defined(CONFIG_SOC_LPC55S69_CPU0)