diff --git a/dts/arm/nxp/nxp_s32k146.dtsi b/dts/arm/nxp/nxp_s32k146.dtsi
index 834c0ad360d..9ca9c63635f 100644
--- a/dts/arm/nxp/nxp_s32k146.dtsi
+++ b/dts/arm/nxp/nxp_s32k146.dtsi
@@ -33,6 +33,8 @@
 	};
 };
 
+/delete-node/ &lpi2c1;
+
 &nvic {
 	arm,num-irq-priority-bits = <4>;
 };
diff --git a/dts/arm/nxp/nxp_s32k1xx.dtsi b/dts/arm/nxp/nxp_s32k1xx.dtsi
index e7a49f3fa17..a46c73598a2 100644
--- a/dts/arm/nxp/nxp_s32k1xx.dtsi
+++ b/dts/arm/nxp/nxp_s32k1xx.dtsi
@@ -6,6 +6,7 @@
 
 #include <mem.h>
 #include <arm/armv7-m.dtsi>
+#include <zephyr/dt-bindings/i2c/i2c.h>
 
 / {
 	cpus {
@@ -80,6 +81,27 @@
 			status = "okay";
 		};
 
+		lpi2c0: i2c@40066000 {
+			compatible = "nxp,imx-lpi2c";
+			clock-frequency = <I2C_BITRATE_STANDARD>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40066000 0x1000>;
+			interrupts = <24 0>;
+			clocks = <&clock NXP_S32_LPI2C0_CLK>;
+			status = "disabled";
+		};
+
+		lpi2c1: i2c@40067000 {
+			compatible = "nxp,imx-lpi2c";
+			clock-frequency = <I2C_BITRATE_STANDARD>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40067000 0x1000>;
+			interrupts = <25 0>;
+			status = "disabled";
+		};
+
 		lpuart0: uart@4006a000 {
 			compatible = "nxp,kinetis-lpuart";
 			reg = <0x4006a000 0x1000>;
diff --git a/soc/arm/nxp_s32/s32k1/Kconfig.series b/soc/arm/nxp_s32/s32k1/Kconfig.series
index e12df1c488f..7359038ee54 100644
--- a/soc/arm/nxp_s32/s32k1/Kconfig.series
+++ b/soc/arm/nxp_s32/s32k1/Kconfig.series
@@ -14,5 +14,6 @@ config SOC_SERIES_S32K1XX
 	select MPU_ALLOW_FLASH_WRITE if !XIP
 	select CLOCK_CONTROL
 	select HAS_MCUX_LPUART
+	select HAS_MCUX_LPI2C
 	help
 	  Enable support for NXP S32K1XX MCU series.