From 3ad57e30301a4b6e3475da5bd1d6f1e7682287bb Mon Sep 17 00:00:00 2001 From: Joakim Andersson Date: Wed, 15 May 2024 16:56:24 +0200 Subject: [PATCH] drivers: spi_bitbang: Fix timing in SPI bitbang driver Fix timing in SPI bitbang driver. The issue occurs with CPHA=1 when the input data is changed immediately after the clock shift on the last bit of the read. Because we read the input bit after changing the clock, this bit becomes invalid. Instead of doing wait, clock-change, read. Do wait, read, clock-change. Signed-off-by: Joakim Andersson --- drivers/spi/spi_bitbang.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/spi/spi_bitbang.c b/drivers/spi/spi_bitbang.c index cffd25abd9a..15ab576a139 100644 --- a/drivers/spi/spi_bitbang.c +++ b/drivers/spi/spi_bitbang.c @@ -177,22 +177,22 @@ static int spi_bitbang_transceive(const struct device *dev, k_busy_wait(wait_us); - /* first clock edge */ - gpio_pin_set_dt(&info->clk_gpio, !clock_state); - if (!loop && do_read && !cpha) { b = gpio_pin_get_dt(miso); } - k_busy_wait(wait_us); + /* first (leading) clock edge */ + gpio_pin_set_dt(&info->clk_gpio, !clock_state); - /* second clock edge */ - gpio_pin_set_dt(&info->clk_gpio, clock_state); + k_busy_wait(wait_us); if (!loop && do_read && cpha) { b = gpio_pin_get_dt(miso); } + /* second (trailing) clock edge */ + gpio_pin_set_dt(&info->clk_gpio, clock_state); + if (loop) { b = d; }