From 3a967f92c33d9f9b0a4a0653007e2f5814a3ef6b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ya=C3=ABl=20Boutreux?= Date: Thu, 1 Aug 2019 13:57:30 +0200 Subject: [PATCH] soc: arm: st_stm32: stm32mp1: Add SPI support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add SPI support for STM32MP1x SoC. Signed-off-by: Yaël Boutreux Signed-off-by: Arnaud Pouliquen Signed-off-by: Alexandre Torgue --- drivers/pinmux/stm32/pinmux_stm32mp1x.h | 18 +++++++ dts/arm/st/mp1/stm32mp157.dtsi | 50 +++++++++++++++++++ soc/arm/st_stm32/stm32mp1/dts_fixup.h | 65 +++++++++++++++++++++++++ 3 files changed, 133 insertions(+) diff --git a/drivers/pinmux/stm32/pinmux_stm32mp1x.h b/drivers/pinmux/stm32/pinmux_stm32mp1x.h index 2b30e2700f7..b92b8ffaf1f 100644 --- a/drivers/pinmux/stm32/pinmux_stm32mp1x.h +++ b/drivers/pinmux/stm32/pinmux_stm32mp1x.h @@ -38,5 +38,23 @@ (STM32_PINMUX_ALT_FUNC_7 | STM32_PUSHPULL_PULLUP) #define STM32MP1X_PINMUX_FUNC_PE10_UART7_CTS \ (STM32_PINMUX_ALT_FUNC_7 | STM32_PUSHPULL_PULLUP) +#define STM32MP1X_PINMUX_FUNC_PE11_SPI4_NSS \ + (STM32_PINMUX_ALT_FUNC_5 | STM32_PUSHPULL_NOPULL) +#define STM32MP1X_PINMUX_FUNC_PE12_SPI4_SCK \ + (STM32_PINMUX_ALT_FUNC_5 | STM32_PUSHPULL_NOPULL) +#define STM32MP1X_PINMUX_FUNC_PE13_SPI4_MISO \ + (STM32_PINMUX_ALT_FUNC_5 | STM32_PUSHPULL_NOPULL) +#define STM32MP1X_PINMUX_FUNC_PE14_SPI4_MOSI \ + (STM32_PINMUX_ALT_FUNC_5 | STM32_PUSHPULL_NOPULL) + +/* Port F */ +#define STM32MP1X_PINMUX_FUNC_PF6_SPI5_NSS \ + (STM32_PINMUX_ALT_FUNC_5 | STM32_PUSHPULL_NOPULL) +#define STM32MP1X_PINMUX_FUNC_PF7_SPI5_SCK \ + (STM32_PINMUX_ALT_FUNC_5 | STM32_PUSHPULL_NOPULL) +#define STM32MP1X_PINMUX_FUNC_PF8_SPI5_MISO \ + (STM32_PINMUX_ALT_FUNC_5 | STM32_PUSHPULL_NOPULL) +#define STM32MP1X_PINMUX_FUNC_PF9_SPI5_MOSI \ + (STM32_PINMUX_ALT_FUNC_5 | STM32_PUSHPULL_NOPULL) #endif /* ZEPHYR_DRIVERS_PINMUX_STM32_PINMUX_STM32MP1X_H_ */ diff --git a/dts/arm/st/mp1/stm32mp157.dtsi b/dts/arm/st/mp1/stm32mp157.dtsi index 294ae2e6cc9..bd9939d4b15 100644 --- a/dts/arm/st/mp1/stm32mp157.dtsi +++ b/dts/arm/st/mp1/stm32mp157.dtsi @@ -148,6 +148,56 @@ }; }; + spi1: spi@44004000 { + compatible = "st,stm32-spi-fifo"; + reg = <0x44004000 0x400>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&rcc STM32_CLOCK_BUS_APB2 0x100>; + interrupts = <35 5>; + label = "SPI_1"; + }; + + spi2: spi@4400b000 { + compatible = "st,stm32-spi-fifo"; + reg = <0x4400b000 0x400>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&rcc STM32_CLOCK_BUS_APB1 0x800>; + interrupts = <36 5>; + label = "SPI_2"; + }; + + spi3: spi@4400c000 { + compatible = "st,stm32-spi-fifo"; + reg = <0x4400c000 0x400>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&rcc STM32_CLOCK_BUS_APB1 0x1000>; + interrupts = <51 5>; + label = "SPI_3"; + }; + + spi4: spi@44005000 { + compatible = "st,stm32-spi-fifo"; + reg = <0x44005000 0x400>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&rcc STM32_CLOCK_BUS_APB2 0x200>; + interrupts = <84 5>; + label = "SPI_4"; + }; + + spi5: spi@44009000 { + compatible = "st,stm32-spi-fifo"; + reg = <0x44009000 0x400>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&rcc STM32_CLOCK_BUS_APB2 0x400>; + interrupts = <85 5>; + label = "SPI_5"; + }; + usart2: serial@4000e000 { compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x4000e000 0x400>; diff --git a/soc/arm/st_stm32/stm32mp1/dts_fixup.h b/soc/arm/st_stm32/stm32mp1/dts_fixup.h index 23adcf8622b..4c4d9953397 100644 --- a/soc/arm/st_stm32/stm32mp1/dts_fixup.h +++ b/soc/arm/st_stm32/stm32mp1/dts_fixup.h @@ -195,6 +195,71 @@ #define DT_GPIO_STM32_GPIOK_CLOCK_BUS \ DT_ST_STM32_GPIO_5000C000_CLOCK_BUS +#define DT_SPI_1_BASE_ADDRESS \ + DT_ST_STM32_SPI_FIFO_44004000_BASE_ADDRESS +#define DT_SPI_1_IRQ_PRI \ + DT_ST_STM32_SPI_FIFO_44004000_IRQ_0_PRIORITY +#define DT_SPI_1_NAME \ + DT_ST_STM32_SPI_FIFO_44004000_LABEL +#define DT_SPI_1_IRQ \ + DT_ST_STM32_SPI_FIFO_44004000_IRQ_0 +#define DT_SPI_1_CLOCK_BITS \ + DT_ST_STM32_SPI_FIFO_44004000_CLOCK_BITS +#define DT_SPI_1_CLOCK_BUS \ + DT_ST_STM32_SPI_FIFO_44004000_CLOCK_BUS + +#define DT_SPI_2_BASE_ADDRESS \ + DT_ST_STM32_SPI_FIFO_4400B000_BASE_ADDRESS +#define DT_SPI_2_IRQ_PRI \ + DT_ST_STM32_SPI_FIFO_4400B000_IRQ_0_PRIORITY +#define DT_SPI_2_NAME \ + DT_ST_STM32_SPI_FIFO_4400B000_LABEL +#define DT_SPI_2_IRQ \ + DT_ST_STM32_SPI_FIFO_4400B000_IRQ_0 +#define DT_SPI_2_CLOCK_BITS \ + DT_ST_STM32_SPI_FIFO_4400B000_CLOCK_BITS +#define DT_SPI_2_CLOCK_BUS \ + DT_ST_STM32_SPI_FIFO_4400B000_CLOCK_BUS + +#define DT_SPI_3_BASE_ADDRESS \ + DT_ST_STM32_SPI_FIFO_4400C000_BASE_ADDRESS +#define DT_SPI_3_IRQ_PRI \ + DT_ST_STM32_SPI_FIFO_4400C000_IRQ_0_PRIORITY +#define DT_SPI_3_NAME \ + DT_ST_STM32_SPI_FIFO_4400C000_LABEL +#define DT_SPI_3_IRQ \ + DT_ST_STM32_SPI_FIFO_4400C000_IRQ_0 +#define DT_SPI_3_CLOCK_BITS \ + DT_ST_STM32_SPI_FIFO_4400C000_CLOCK_BITS +#define DT_SPI_3_CLOCK_BUS \ + DT_ST_STM32_SPI_FIFO_4400C000_CLOCK_BUS + +#define DT_SPI_4_BASE_ADDRESS \ + DT_ST_STM32_SPI_FIFO_44005000_BASE_ADDRESS +#define DT_SPI_4_IRQ_PRI \ + DT_ST_STM32_SPI_FIFO_44005000_IRQ_0_PRIORITY +#define DT_SPI_4_NAME \ + DT_ST_STM32_SPI_FIFO_44005000_LABEL +#define DT_SPI_4_IRQ \ + DT_ST_STM32_SPI_FIFO_44005000_IRQ_0 +#define DT_SPI_4_CLOCK_BITS \ + DT_ST_STM32_SPI_FIFO_44005000_CLOCK_BITS +#define DT_SPI_4_CLOCK_BUS \ + DT_ST_STM32_SPI_FIFO_44005000_CLOCK_BUS + +#define DT_SPI_5_BASE_ADDRESS \ + DT_ST_STM32_SPI_FIFO_44009000_BASE_ADDRESS +#define DT_SPI_5_IRQ_PRI \ + DT_ST_STM32_SPI_FIFO_44009000_IRQ_0_PRIORITY +#define DT_SPI_5_NAME \ + DT_ST_STM32_SPI_FIFO_44009000_LABEL +#define DT_SPI_5_IRQ \ + DT_ST_STM32_SPI_FIFO_44009000_IRQ_0 +#define DT_SPI_5_CLOCK_BITS \ + DT_ST_STM32_SPI_FIFO_44009000_CLOCK_BITS +#define DT_SPI_5_CLOCK_BUS \ + DT_ST_STM32_SPI_FIFO_40009000_CLOCK_BUS + #define DT_UART_STM32_USART_2_BASE_ADDRESS \ DT_ST_STM32_USART_4000E000_BASE_ADDRESS #define DT_UART_STM32_USART_2_BAUD_RATE \