soc: arm: nxp: Add LPC51U68 support.

Add initial support for NXP LPC51U68 SOC series

Signed-off-by: Navin Sankar Velliangiri <navin@linumiz.com>

soc/arm/nxp_lpc/Kconfig

@@ -17,5 +17,6 @@ config SOC_PART_NUMBER
 	default SOC_PART_NUMBER_LPC54XXX if SOC_SERIES_LPC54XXX
 	default SOC_PART_NUMBER_LPC55XXX if SOC_SERIES_LPC55XXX
 	default SOC_PART_NUMBER_LPC11U6X if SOC_SERIES_LPC11U6X
+	default SOC_PART_NUMBER_LPC51U68 if SOC_SERIES_LPC51U68
 
 endif # SOC_FAMILY_LPC

soc/arm/nxp_lpc/lpc51u68/CMakeLists.txt

@@ -0,0 +1,13 @@
+#
+# Copyright (c) 2021 metraTec GmbH
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+zephyr_library()
+
+zephyr_library_sources(soc.c)
+
+zephyr_library_include_directories(
+  ${ZEPHYR_BASE}/kernel/include
+  ${ZEPHYR_BASE}/arch/${ARCH}/include
+  )

soc/arm/nxp_lpc/lpc51u68/Kconfig.defconfig.series

@@ -0,0 +1,22 @@
+# LPC51U68 series configuration options
+
+# Copyright (c) 2021 metraTec GmbH
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_SERIES_LPC51U68
+
+config SOC_SERIES
+	default "lpc51u68"
+
+config NUM_IRQS
+	# must be >= the highest interrupt number used.
+	default 32
+
+config SOC
+	default "lpc51u68"
+
+config SOC_FLASH_LPC
+	default y
+	depends on FLASH
+
+endif

soc/arm/nxp_lpc/lpc51u68/Kconfig.series

@@ -0,0 +1,17 @@
+# LPC LPC51U68 Series
+
+# Copyright (c) 2021 metraTec GmbH
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_LPC51U68
+	bool "LPC LPC51U68 Series MCU"
+	select ARM
+	select CPU_CORTEX_M0PLUS
+	select HAS_MCUX
+	select HAS_MCUX_FLEXCOMM
+	select HAS_MCUX_SYSCON
+	select HAS_MCUX_SCTIMER
+	select SOC_FAMILY_LPC
+	select CPU_CORTEX_M_HAS_SYSTICK
+	help
+	  Enable support for LPC LPC51U68 MCU Series

soc/arm/nxp_lpc/lpc51u68/Kconfig.soc

@@ -0,0 +1,27 @@
+# LPC LPC51U68 MCU line
+
+# Copyright (c) 2021 metraTec GmbH
+# SPDX-License Identifier: Apache-2.0
+
+config SOC_LPC51U68
+	bool "SOC_LPC51U68"
+	depends on SOC_SERIES_LPC51U68
+	select CLOCK_CONTROL
+
+if SOC_SERIES_LPC51U68
+
+config SOC_PART_NUMBER_LPC51U68JBD48
+	bool
+config SOC_PART_NUMBER_LPC51U68JBD64
+	bool
+
+config SOC_PART_NUMBER_LPC51U68
+	string
+	default "LPC51U68JBD48" if SOC_PART_NUMBER_LPC51U68JBD48
+	default "LPC51U68JBD64" if SOC_PART_NUMBER_LPC51U68JBD64
+	help
+	  This string holds the full part number of the SoC. It is a hidden
+	  option that you should not set directly. The part number selection
+	  choice defines the default value for this string.
+
+endif # SOC_SERIES_LPC51U68

soc/arm/nxp_lpc/lpc51u68/linker.ld

@@ -0,0 +1,7 @@
+/*
+ * Copyright (c) 2021 metraTec GmbH
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/arch/arm/aarch32/cortex_m/scripts/linker.ld>

soc/arm/nxp_lpc/lpc51u68/pinctrl_soc.h

@@ -0,0 +1,67 @@
+/*
+ * Copyright 2022 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_SOC_ARM_NXP_LPC_51U68_PINCTRL_SOC_H_
+#define ZEPHYR_SOC_ARM_NXP_LPC_51U68_PINCTRL_SOC_H_
+
+#include <zephyr/devicetree.h>
+#include <zephyr/types.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @cond INTERNAL_HIDDEN */
+
+typedef uint32_t pinctrl_soc_pin_t;
+
+#define Z_PINCTRL_IOCON_PINCFG(node_id)						\
+	(IF_ENABLED(DT_PROP(node_id, bias_pull_down), (IOCON_PIO_MODE(0x1) |))	\
+	IF_ENABLED(DT_PROP(node_id, bias_pull_up), (IOCON_PIO_MODE(0x2) |))	\
+	IF_ENABLED(DT_PROP(node_id, drive_push_pull), (IOCON_PIO_MODE(0x3) |))	\
+	IOCON_PIO_INVERT(DT_PROP(node_id, nxp_invert)) |			\
+	IOCON_PIO_DIGIMODE(!DT_PROP(node_id, nxp_analog_mode)) |		\
+	IOCON_PIO_FILTEROFF(!DT_NODE_HAS_PROP(node_id, nxp_digital_filter)) |	\
+	IOCON_PIO_SLEW(DT_ENUM_IDX(node_id, slew_rate)) |			\
+	IOCON_PIO_OD(DT_PROP(node_id, drive_open_drain)) |			\
+	IOCON_PIO_I2CSLEW(!DT_PROP(node_id, nxp_i2c_mode)) |			\
+	IOCON_PIO_I2CDRIVE(DT_ENUM_IDX_OR(node_id, nxp_i2c_speed, 0)) |			\
+	IOCON_PIO_I2CFILTER(DT_ENUM_IDX_OR(node_id, nxp_i2c_filter, 0)))
+
+/* Mask for digital type pin configuration register */
+#define Z_PINCTRL_IOCON_D_PIN_MASK (IOCON_PIO_OD_MASK |				\
+	IOCON_PIO_DIGIMODE_MASK | IOCON_PIO_INVERT_MASK | IOCON_PIO_SLEW_MASK |	\
+	IOCON_PIO_MODE_MASK | IOCON_PIO_FUNC_MASK)
+
+/* LPC51U68 does not have analog type pins */
+#define Z_PINCTRL_IOCON_A_PIN_MASK						\
+	(Z_PINCTRL_IOCON_D_PIN_MASK)
+
+/* Mask for i2c type pin configuration register */
+#define Z_PINCTRL_IOCON_I_PIN_MASK (IOCON_PIO_FUNC_MASK |			\
+	IOCON_PIO_I2CSLEW_MASK | IOCON_PIO_INVERT_MASK |			\
+	IOCON_PIO_DIGIMODE_MASK | IOCON_PIO_FILTEROFF_MASK |			\
+	IOCON_PIO_I2CDRIVE_MASK | IOCON_PIO_I2CFILTER_MASK)
+
+#define Z_PINCTRL_STATE_PIN_INIT(group, pin_prop, idx)				\
+	DT_PROP_BY_IDX(group, pin_prop, idx) | Z_PINCTRL_IOCON_PINCFG(group),
+
+/**
+ * @brief Utility macro to initialize state pins contained in a given property.
+ *
+ * @param node_id Node identifier.
+ * @param prop Property name describing state pins.
+ */
+#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop)			       \
+	{DT_FOREACH_CHILD_VARGS(DT_PHANDLE(node_id, prop),		       \
+				DT_FOREACH_PROP_ELEM, pinmux,		       \
+				Z_PINCTRL_STATE_PIN_INIT)}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ZEPHYR_SOC_ARM_NXP_LPC_51U68_PINCTRL_SOC_H_ */

soc/arm/nxp_lpc/lpc51u68/soc.c

@@ -0,0 +1,55 @@
+/*
+ * Copyright (c) 2021 metraTec GmbH
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/kernel.h>
+#include <zephyr/device.h>
+#include <zephyr/init.h>
+#include <soc.h>
+#include <fsl_power.h>
+#include <fsl_clock.h>
+
+int soc_init(const struct device *arg)
+{
+	POWER_DisablePD(kPDRUNCFG_PD_FRO_EN);
+	CLOCK_SetupFROClocking(12000000U);
+	CLOCK_AttachClk(kFRO12M_to_MAIN_CLK);
+
+	CLOCK_SetFLASHAccessCyclesForFreq(12000000U);
+
+	CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false);
+	CLOCK_SetClkDiv(kCLOCK_DivSystickClk, 0U, true);
+	CLOCK_SetClkDiv(kCLOCK_DivSystickClk, 1U, false);
+
+	CLOCK_AttachClk(kFRO12M_to_MAIN_CLK);
+
+	/* Attach 12 MHz clock to flexcomm0 */
+	CLOCK_AttachClk(kFRO12M_to_FLEXCOMM0);
+
+#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm4), nxp_lpc_i2c, okay)
+	/* attach 12 MHz clock for flexcomm4 */
+	CLOCK_AttachClk(kFRO12M_to_FLEXCOMM4);
+
+	/* reset FLEXCOMM for I2C */
+	RESET_PeripheralReset(kFC4_RST_SHIFT_RSTn);
+#endif
+
+#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm5), nxp_lpc_spi, okay)
+	/* attach 12MHz clock to flexcomm5 */
+	CLOCK_AttachClk(kFRO12M_to_FLEXCOMM5);
+
+	/* reset FLEXCOMM for SPI */
+	RESET_PeripheralReset(kFC5_RST_SHIFT_RSTn);
+#endif
+
+	POWER_DisablePD(kPDRUNCFG_PD_ADC0);
+	POWER_DisablePD(kPDRUNCFG_PD_VD7_ENA);
+	POWER_DisablePD(kPDRUNCFG_PD_VREFP_SW);
+	POWER_DisablePD(kPDRUNCFG_PD_TEMPS);
+
+	return 0;
+}
+
+SYS_INIT(soc_init, PRE_KERNEL_1, 0);

soc/arm/nxp_lpc/lpc51u68/soc.h

@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2021 metraTec GmbH
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _SOC_H_
+#define _SOC_H_
+
+#ifndef _ASMLANGUAGE
+#include <zephyr/sys/util.h>
+
+#endif /* !_ASMLANGUAGE*/
+
+#define IOCON_PIO_DIGITAL_EN	0x80u
+#define IOCON_PIO_FUNC0		0x00u
+#define IOCON_PIO_FUNC1		0x01u
+#define IOCON_PIO_FUNC2		0x02u
+#define IOCON_PIO_FUNC3		0x03u
+#define IOCON_PIO_FUNC4		0x04u
+#define IOCON_PIO_I2CDRIVE_LOW	0x00u
+#define IOCON_PIO_I2CFILTER_EN	0x00u
+#define IOCON_PIO_I2CSLEW_I2C	0x00u
+#define IOCON_PIO_INPFILT_OFF	0x0100u
+#define IOCON_PIO_OPENDRAIN_DI	0x00u
+#define IOCON_PIO_INV_DI	0x00u
+#define IOCON_PIO_MODE_INACT	0x00u
+#define IOCON_PIO_SLEW_STANDARD	0x00u
+#define IOCON_PIO_MODE_PULLUP	0x10u
+#define IOCON_PIO_MODE_PULLDOWN	0x08u
+
+#endif /* _SOC_H_ */