boards: nxp/frdm_mcxn947: Support sai for NXP frdm_mcxn947

Support sai for NXP frdm_mcxn947.

Signed-off-by: Qiang Zhang <qiang.zhang_6@nxp.com>

boards/nxp/frdm_mcxn947/board.c

@@ -131,21 +131,18 @@ static int frdm_mcxn947_init(void)
 
 	CLOCK_SetupExtClocking(BOARD_XTAL0_CLK_HZ);
 
-#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(flexcan0))
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(sai0)) || DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(sai1))
-	/* Set up PLL1 for 80 MHz FlexCAN clock */
+	/* < Set up PLL1 */
-	const pll_setup_t pll1Setup = {
+	const pll_setup_t pll1_Setup = {
-		.pllctrl = SCG_SPLLCTRL_SOURCE(1U) | SCG_SPLLCTRL_SELI(27U) |
+		.pllctrl = SCG_SPLLCTRL_SOURCE(1U) | SCG_SPLLCTRL_SELI(3U) |
-			   SCG_SPLLCTRL_SELP(13U),
+				 SCG_SPLLCTRL_SELP(1U),
-		.pllndiv = SCG_SPLLNDIV_NDIV(3U),
+		.pllndiv = SCG_SPLLNDIV_NDIV(25U),
-		.pllpdiv = SCG_SPLLPDIV_PDIV(1U),
+		.pllpdiv = SCG_SPLLPDIV_PDIV(10U),
-		.pllmdiv = SCG_SPLLMDIV_MDIV(10U),
+		.pllmdiv = SCG_SPLLMDIV_MDIV(256U),
-		.pllRate = 80000000U
+		.pllRate = 24576000U};
-	};
 
 	/* Configure PLL1 to the desired values */
-	CLOCK_SetPLL1Freq(&pll1Setup);
+	CLOCK_SetPLL1Freq(&pll1_Setup);
-	/* PLL1 Monitor is disabled */
-	CLOCK_SetPll1MonitorMode(kSCG_Pll1MonitorDisable);
 	/* Set PLL1 CLK0 divider to value 1 */
 	CLOCK_SetClkDiv(kCLOCK_DivPLL1Clk0, 1U);
 #endif
@@ -250,7 +247,7 @@ static int frdm_mcxn947_init(void)
 
 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(flexcan0))
 	CLOCK_SetClkDiv(kCLOCK_DivFlexcan0Clk, 1U);
-	CLOCK_AttachClk(kPLL1_CLK0_to_FLEXCAN0);
+	CLOCK_AttachClk(kFRO_HF_to_FLEXCAN0);
 #endif
 
 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(usdhc0))
@@ -383,6 +380,18 @@ static int frdm_mcxn947_init(void)
 	CLOCK_AttachClk(kFRO_HF_to_SCT);
 #endif
 
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(sai0))
+	CLOCK_SetClkDiv(kCLOCK_DivSai0Clk, 1u);
+	CLOCK_AttachClk(kPLL1_CLK0_to_SAI0);
+	CLOCK_EnableClock(kCLOCK_Sai0);
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(sai1))
+	CLOCK_SetClkDiv(kCLOCK_DivSai1Clk, 1u);
+	CLOCK_AttachClk(kPLL1_CLK0_to_SAI1);
+	CLOCK_EnableClock(kCLOCK_Sai1);
+#endif
+
 	/* Set SystemCoreClock variable. */
 	SystemCoreClock = CLOCK_INIT_CORE_CLOCK;
 

boards/nxp/frdm_mcxn947/doc/index.rst

@@ -97,6 +97,8 @@ The FRDM-MCXN947 board configuration supports the following hardware features:
 +-----------+------------+-------------------------------------+
 | FLEXIO    | on-chip    | flexio                              |
 +-----------+------------+-------------------------------------+
+| SAI       | on-chip    | i2s                                 |
++-----------+------------+-------------------------------------+
 | DISPLAY   | on-chip    | flexio; MIPI-DBI. Tested with       |
 |           |            | :ref:`lcd_par_s035`                 |
 +-----------+------------+-------------------------------------+

boards/nxp/frdm_mcxn947/frdm_mcxn947-pinctrl.dtsi

@@ -92,6 +92,31 @@
 		};
 	};
 
+	pinmux_sai1: pinmux_sai1 {
+		group0 {
+			pinmux = <SAI1_TX_BCLK_PIO3_16>,
+				<SAI1_TX_FS_PIO3_17>,
+				<SAI1_TXD0_PIO3_20>,
+				<SAI1_RX_FS_PIO3_19>,
+				<SAI1_RX_BCLK_PIO3_18>,
+				<SAI1_RXD0_PIO3_21>;
+			drive-strength = "high";
+			slew-rate = "fast";
+			input-enable;
+		};
+	};
+
+	pinmux_sai0: pinmux_sai0 {
+		group0 {
+			pinmux = <SAI0_TXD0_PIO2_2>,
+				<SAI0_TX_BCLK_PIO2_6>,
+				<SAI0_TX_FS_PIO2_7>;
+			drive-strength = "high";
+			slew-rate = "fast";
+			input-enable;
+		};
+	};
+
 	pinmux_enet_qos: pinmux_enet_qos {
 		mdio_group {
 			pinmux = <ENET0_MDC_PIO1_20>,

boards/nxp/frdm_mcxn947/frdm_mcxn947.dtsi

@@ -206,6 +206,16 @@ nxp_8080_touch_panel_i2c: &flexcomm2_lpi2c2 {
 	pinctrl-names = "default";
 };
 
+&sai1 {
+	pinctrl-0 = <&pinmux_sai1>;
+	pinctrl-names = "default";
+};
+
+&sai0 {
+	pinctrl-0 = <&pinmux_sai0>;
+	pinctrl-names = "default";
+};
+
 &enet {
 	pinctrl-0 = <&pinmux_enet_qos>;
 	pinctrl-names = "default";

boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0.dtsi

@@ -233,3 +233,10 @@ zephyr_udc0: &usb1 {
 &sc_timer {
 	status = "okay";
 };
+
+&sai1 {
+	status = "okay";
+};
+&sai0 {
+	status = "okay";
+};

boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0.yaml

@@ -23,6 +23,7 @@ supported:
   - flash
   - gpio
   - i2c
+  - i2s
   - i3c
   - pwm
   - regulator

soc/nxp/mcx/mcxn/Kconfig.defconfig

@@ -27,4 +27,9 @@ config SYS_CLOCK_HW_CYCLES_PER_SEC
 config FLASH_FILL_BUFFER_SIZE
 	default 128
 
+# The existing SAI diver cannot initialize the PLL on the board,
+# so the PLL settings will not be performed in the driver.
+config I2S_HAS_PLL_SETTING
+	default n
+
 endif # SOC_SERIES_MCXN