tests: drivers: clock_control: stm32_devices: split test
Split STM32 device clock configuration file so that each driver has its own tests in its own file Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
This commit is contained in:
Guillaume Gautier
Carles Cufí
parent
6f525f33a4
commit
3a0b00272b
4 changed files with 346 additions and 314 deletions
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@ -11,8 +11,6 @@
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#include <zephyr/logging/log.h>
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LOG_MODULE_REGISTER(test);
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#define DT_NO_CLOCK 0xFFFFU
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/* Not device related, but keep it to ensure core clock config is correct */
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ZTEST(stm32_common_devices_clocks, test_sysclk_freq)
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{
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@ -25,316 +23,4 @@ ZTEST(stm32_common_devices_clocks, test_sysclk_freq)
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CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC, soc_sys_clk_freq);
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}
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#if !defined(CONFIG_SOC_SERIES_STM32F4X)
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(i2c1), okay)
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#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32_i2c_v1)
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#define DT_DRV_COMPAT st_stm32_i2c_v1
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#elif DT_HAS_COMPAT_STATUS_OKAY(st_stm32_i2c_v2)
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#define DT_DRV_COMPAT st_stm32_i2c_v2
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#endif
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#if STM32_DT_INST_DEV_DOMAIN_CLOCK_SUPPORT
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#define STM32_I2C_DOMAIN_CLOCK_SUPPORT 1
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#else
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#define STM32_I2C_DOMAIN_CLOCK_SUPPORT 0
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#endif
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static void i2c_set_clock(const struct stm32_pclken *clk)
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{
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uint32_t dev_dt_clk_freq, dev_actual_clk_freq;
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/* Test clock_on(domain_clk) */
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int r = clock_control_configure(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE),
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(clock_control_subsys_t) clk,
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NULL);
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zassert_true((r == 0), "Could not enable I2C domain clock");
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TC_PRINT("I2C1 domain clock configured\n");
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/* Test clock source */
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uint32_t dev_actual_clk_src = __HAL_RCC_GET_I2C1_SOURCE();
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if (clk->bus == STM32_SRC_HSI) {
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zassert_equal(dev_actual_clk_src, RCC_I2C1CLKSOURCE_HSI,
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"Expected I2C src: HSI (0x%lx). Actual I2C src: 0x%x",
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RCC_I2C1CLKSOURCE_HSI, dev_actual_clk_src);
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} else if (clk->bus == STM32_SRC_SYSCLK) {
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zassert_equal(dev_actual_clk_src, RCC_I2C1CLKSOURCE_SYSCLK,
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"Expected I2C src: SYSCLK (0x%lx). Actual I2C src: 0x%x",
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RCC_I2C1CLKSOURCE_SYSCLK, dev_actual_clk_src);
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} else {
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zassert_true(0, "Unexpected domain clk (0x%x)", dev_actual_clk_src);
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}
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/* Test get_rate(srce clk) */
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r = clock_control_get_rate(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE),
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(clock_control_subsys_t) clk,
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&dev_dt_clk_freq);
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zassert_true((r == 0), "Could not get I2C clk srce freq");
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dev_actual_clk_freq = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_I2C1);
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zassert_equal(dev_dt_clk_freq, dev_actual_clk_freq,
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"Expected freq: %d Hz. Actual clk: %d Hz",
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dev_dt_clk_freq, dev_actual_clk_freq);
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TC_PRINT("I2C1 clock source rate: %d Hz\n", dev_dt_clk_freq);
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}
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ZTEST(stm32_common_devices_clocks, test_i2c_clk_config)
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{
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static const struct stm32_pclken pclken[] = STM32_DT_CLOCKS(DT_NODELABEL(i2c1));
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uint32_t dev_dt_clk_freq, dev_actual_clk_freq;
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int r;
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/* Test clock_on(gating clock) */
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r = clock_control_on(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE),
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(clock_control_subsys_t) &pclken[0]);
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zassert_true((r == 0), "Could not enable I2C gating clock");
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zassert_true(__HAL_RCC_I2C1_IS_CLK_ENABLED(), "I2C1 gating clock should be on");
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TC_PRINT("I2C1 gating clock on\n");
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if (IS_ENABLED(STM32_I2C_DOMAIN_CLOCK_SUPPORT) && DT_NUM_CLOCKS(DT_NODELABEL(i2c1)) > 1) {
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if (DT_NUM_CLOCKS(DT_NODELABEL(i2c1)) > 2) {
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/* set a dummy clock first, to check if the register is set correctly even
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* if not in reset state
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*/
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i2c_set_clock(&pclken[2]);
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}
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i2c_set_clock(&pclken[1]);
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} else {
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zassert_true((DT_NUM_CLOCKS(DT_NODELABEL(i2c1)) == 1), "test config issue");
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/* No domain clock available, get rate from gating clock */
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/* Test get_rate */
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r = clock_control_get_rate(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE),
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(clock_control_subsys_t) &pclken[0],
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&dev_dt_clk_freq);
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zassert_true((r == 0), "Could not get I2C clk freq");
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dev_actual_clk_freq = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_I2C1);
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zassert_equal(dev_dt_clk_freq, dev_actual_clk_freq,
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"Expected freq: %d Hz. Actual freq: %d Hz",
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dev_dt_clk_freq, dev_actual_clk_freq);
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TC_PRINT("I2C1 clock source rate: %d Hz\n", dev_dt_clk_freq);
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}
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/* Test clock_off(gating clk) */
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r = clock_control_off(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE),
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(clock_control_subsys_t) &pclken[0]);
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zassert_true((r == 0), "Could not disable I2C gating clk");
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zassert_true(!__HAL_RCC_I2C1_IS_CLK_ENABLED(), "I2C1 gating clk should be off");
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TC_PRINT("I2C1 gating clk off\n");
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/* Test clock_off(srce) */
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/* Not supported today */
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}
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#endif
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#endif
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(lptim1), okay)
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#undef DT_DRV_COMPAT
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#define DT_DRV_COMPAT st_stm32_lptim
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#if STM32_DT_INST_DEV_DOMAIN_CLOCK_SUPPORT
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#define STM32_LPTIM_OPT_CLOCK_SUPPORT 1
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#else
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#define STM32_LPTIM_OPT_CLOCK_SUPPORT 0
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#endif
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ZTEST(stm32_common_devices_clocks, test_lptim_clk_config)
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{
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static const struct stm32_pclken pclken[] = STM32_DT_CLOCKS(DT_NODELABEL(lptim1));
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uint32_t dev_dt_clk_freq, dev_actual_clk_freq;
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uint32_t dev_actual_clk_src;
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int r;
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/* Test clock_on(gating clock) */
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r = clock_control_on(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE),
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(clock_control_subsys_t) &pclken[0]);
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zassert_true((r == 0), "Could not enable LPTIM gating clock");
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zassert_true(__HAL_RCC_LPTIM1_IS_CLK_ENABLED(), "LPTIM1 gating clock should be on");
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TC_PRINT("LPTIM1 gating clock on\n");
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if (IS_ENABLED(STM32_LPTIM_OPT_CLOCK_SUPPORT) && DT_NUM_CLOCKS(DT_NODELABEL(lptim1)) > 1) {
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/* Test clock_on(domain_clk) */
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r = clock_control_configure(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE),
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(clock_control_subsys_t) &pclken[1],
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NULL);
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zassert_true((r == 0), "Could not enable LPTIM1 domain clock");
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TC_PRINT("LPTIM1 source clock configured\n");
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/* Test clock source */
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dev_actual_clk_src = __HAL_RCC_GET_LPTIM1_SOURCE();
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if (pclken[1].bus == STM32_SRC_LSE) {
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zassert_equal(dev_actual_clk_src, RCC_LPTIM1CLKSOURCE_LSE,
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"Expected LPTIM1 src: LSE (0x%lx). Actual LPTIM1 src: 0x%x",
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RCC_LPTIM1CLKSOURCE_LSE, dev_actual_clk_src);
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} else if (pclken[1].bus == STM32_SRC_LSI) {
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zassert_equal(dev_actual_clk_src, RCC_LPTIM1CLKSOURCE_LSI,
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"Expected LPTIM1 src: LSI (0x%lx). Actual LPTIM1 src: 0x%x",
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RCC_LPTIM1CLKSOURCE_LSI, dev_actual_clk_src);
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} else {
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zassert_true(0, "Unexpected domain clk (%d)", dev_actual_clk_src);
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}
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/* Test get_rate(srce clk) */
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r = clock_control_get_rate(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE),
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(clock_control_subsys_t) &pclken[1],
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&dev_dt_clk_freq);
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zassert_true((r == 0), "Could not get LPTIM1 clk srce freq");
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dev_actual_clk_freq = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_LPTIM1);
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zassert_equal(dev_dt_clk_freq, dev_actual_clk_freq,
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"Expected DT freq: %d Hz. Actual freq: %d Hz",
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dev_dt_clk_freq, dev_actual_clk_freq);
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TC_PRINT("LPTIM1 clock source rate: %d Hz\n", dev_dt_clk_freq);
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} else {
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zassert_true((DT_NUM_CLOCKS(DT_NODELABEL(lptim1)) == 1), "test config issue");
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/* No domain clock available, get rate from gating clock */
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/* Test get_rate */
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r = clock_control_get_rate(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE),
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(clock_control_subsys_t) &pclken[0],
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&dev_dt_clk_freq);
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zassert_true((r == 0), "Could not get LPTIM1 clk freq");
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dev_actual_clk_freq = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_LPTIM1);
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zassert_equal(dev_dt_clk_freq, dev_actual_clk_freq,
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"Expected DT freq: %d Hz. Actual freq: %d Hz",
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dev_dt_clk_freq, dev_actual_clk_freq);
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TC_PRINT("LPTIM1 clock source rate: %d Hz\n", dev_dt_clk_freq);
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}
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/* Test clock_off(reg_clk) */
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r = clock_control_off(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE),
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(clock_control_subsys_t) &pclken[0]);
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zassert_true((r == 0), "Could not disable LPTIM1 gating clk");
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zassert_true(!__HAL_RCC_LPTIM1_IS_CLK_ENABLED(), "LPTIM1 gating clk should be off");
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TC_PRINT("LPTIM1 gating clk off\n");
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/* Test clock_off(domain clk) */
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/* Not supported today */
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}
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#endif
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(adc1), okay)
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#undef DT_DRV_COMPAT
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#define DT_DRV_COMPAT st_stm32_adc
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#if STM32_DT_INST_DEV_DOMAIN_CLOCK_SUPPORT
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#define STM32_ADC_DOMAIN_CLOCK_SUPPORT 1
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#else
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#define STM32_ADC_DOMAIN_CLOCK_SUPPORT 0
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#endif
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#if defined(__HAL_RCC_GET_ADC12_SOURCE)
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#define PERIPHCLK_ADC RCC_PERIPHCLK_ADC12
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#define ADC_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED
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#define GET_ADC_SOURCE __HAL_RCC_GET_ADC12_SOURCE
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#define ADC_SOURCE_SYSCLK RCC_ADC12CLKSOURCE_SYSCLK
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#elif defined(__HAL_RCC_GET_ADC_SOURCE)
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#define PERIPHCLK_ADC RCC_PERIPHCLK_ADC
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#define ADC_IS_CLK_ENABLED __HAL_RCC_ADC_IS_CLK_ENABLED
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#define GET_ADC_SOURCE __HAL_RCC_GET_ADC_SOURCE
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#define ADC_SOURCE_SYSCLK RCC_ADCCLKSOURCE_SYSCLK
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#else
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#define PERIPHCLK_ADC (-1)
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#define ADC_IS_CLK_ENABLED __HAL_RCC_ADC1_IS_CLK_ENABLED
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#define GET_ADC_SOURCE() (-1);
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#endif
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#if defined(RCC_ADC12CLKSOURCE_PLL)
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#define ADC_SOURCE_PLL RCC_ADC12CLKSOURCE_PLL
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#elif defined(RCC_ADCCLKSOURCE_PLLADC)
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#define ADC_SOURCE_PLL RCC_ADCCLKSOURCE_PLLADC
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#elif defined(RCC_ADCCLKSOURCE_PLL)
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#define ADC_SOURCE_PLL RCC_ADCCLKSOURCE_PLL
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#else
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#define ADC_SOURCE_PLL (-1)
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#endif
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ZTEST(stm32_common_devices_clocks, test_adc_clk_config)
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{
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static const struct stm32_pclken pclken[] = STM32_DT_CLOCKS(DT_NODELABEL(adc1));
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uint32_t dev_dt_clk_freq, dev_actual_clk_freq;
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uint32_t dev_actual_clk_src;
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int r;
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/* Test clock_on(gating clock) */
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r = clock_control_on(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE),
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(clock_control_subsys_t) &pclken[0]);
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zassert_true((r == 0), "Could not enable ADC1 gating clock");
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zassert_true(ADC_IS_CLK_ENABLED(), "ADC1 gating clock should be on");
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TC_PRINT("ADC1 gating clock on\n");
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if (IS_ENABLED(STM32_ADC_DOMAIN_CLOCK_SUPPORT) && DT_NUM_CLOCKS(DT_NODELABEL(adc1)) > 1) {
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/* Test clock_on(domain_clk) */
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r = clock_control_configure(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE),
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(clock_control_subsys_t) &pclken[1],
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NULL);
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zassert_true((r == 0), "Could not enable ADC1 domain clock");
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TC_PRINT("ADC1 source clock configured\n");
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/* Test clock source */
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zassert_true((ADC_SOURCE_PLL != -1), "Invalid ADC_SOURCE_PLL defined for target.");
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dev_actual_clk_src = GET_ADC_SOURCE();
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switch (pclken[1].bus) {
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#if defined(STM32_SRC_PLL_P)
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case STM32_SRC_PLL_P:
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zassert_equal(dev_actual_clk_src, ADC_SOURCE_PLL,
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"Expected ADC1 src: PLL (0x%lx). Actual ADC1 src: 0x%x",
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ADC_SOURCE_PLL, dev_actual_clk_src);
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break;
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#endif
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default:
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zassert_true(0, "Unexpected src clk (%d)", dev_actual_clk_src);
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}
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/* Test get_rate(srce clk) */
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r = clock_control_get_rate(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE),
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(clock_control_subsys_t) &pclken[1],
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&dev_dt_clk_freq);
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zassert_true((r == 0), "Could not get ADC1 clk srce freq");
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dev_actual_clk_freq = HAL_RCCEx_GetPeriphCLKFreq(PERIPHCLK_ADC);
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zassert_equal(dev_dt_clk_freq, dev_actual_clk_freq,
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"Expected DT freq: %d Hz. Actual freq: %d Hz",
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dev_dt_clk_freq, dev_actual_clk_freq);
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TC_PRINT("ADC1 clock source rate: %d Hz\n", dev_dt_clk_freq);
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} else {
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zassert_true((DT_NUM_CLOCKS(DT_NODELABEL(adc1)) == 1), "test config issue");
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/* No domain clock available, don't check gating clock as for adc there is no
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* uniform way to verify via hal.
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*/
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TC_PRINT("ADC1 no domain clock defined. Skipped check\n");
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}
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/* Test clock_off(reg_clk) */
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r = clock_control_off(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE),
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(clock_control_subsys_t) &pclken[0]);
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zassert_true((r == 0), "Could not disable ADC1 gating clk");
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zassert_true(!ADC_IS_CLK_ENABLED(), "ADC1 gating clk should be off");
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TC_PRINT("ADC1 gating clk off\n");
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/* Test clock_off(domain clk) */
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/* Not supported today */
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}
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#endif
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ZTEST_SUITE(stm32_common_devices_clocks, NULL, NULL, NULL, NULL, NULL);
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@ -0,0 +1,121 @@
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/*
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* Copyright (c) 2022 Linaro Limited
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/ztest.h>
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#include <soc.h>
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#include <zephyr/drivers/clock_control.h>
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#include <zephyr/drivers/clock_control/stm32_clock_control.h>
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#include <zephyr/logging/log.h>
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(adc1), okay)
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#undef DT_DRV_COMPAT
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#define DT_DRV_COMPAT st_stm32_adc
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#if STM32_DT_INST_DEV_DOMAIN_CLOCK_SUPPORT
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#define STM32_ADC_DOMAIN_CLOCK_SUPPORT 1
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#else
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#define STM32_ADC_DOMAIN_CLOCK_SUPPORT 0
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#endif
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#if defined(__HAL_RCC_GET_ADC12_SOURCE)
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#define PERIPHCLK_ADC RCC_PERIPHCLK_ADC12
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#define ADC_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED
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#define GET_ADC_SOURCE __HAL_RCC_GET_ADC12_SOURCE
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#define ADC_SOURCE_SYSCLK RCC_ADC12CLKSOURCE_SYSCLK
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#elif defined(__HAL_RCC_GET_ADC_SOURCE)
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#define PERIPHCLK_ADC RCC_PERIPHCLK_ADC
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#define ADC_IS_CLK_ENABLED __HAL_RCC_ADC_IS_CLK_ENABLED
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#define GET_ADC_SOURCE __HAL_RCC_GET_ADC_SOURCE
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#define ADC_SOURCE_SYSCLK RCC_ADCCLKSOURCE_SYSCLK
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#else
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#define PERIPHCLK_ADC (-1)
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#define ADC_IS_CLK_ENABLED __HAL_RCC_ADC1_IS_CLK_ENABLED
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#define GET_ADC_SOURCE() (-1);
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#endif
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#if defined(RCC_ADC12CLKSOURCE_PLL)
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#define ADC_SOURCE_PLL RCC_ADC12CLKSOURCE_PLL
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#elif defined(RCC_ADCCLKSOURCE_PLLADC)
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#define ADC_SOURCE_PLL RCC_ADCCLKSOURCE_PLLADC
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#elif defined(RCC_ADCCLKSOURCE_PLL)
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#define ADC_SOURCE_PLL RCC_ADCCLKSOURCE_PLL
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#else
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#define ADC_SOURCE_PLL (-1)
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#endif
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ZTEST(stm32_common_devices_clocks, test_adc_clk_config)
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||||
{
|
||||
static const struct stm32_pclken pclken[] = STM32_DT_CLOCKS(DT_NODELABEL(adc1));
|
||||
|
||||
uint32_t dev_dt_clk_freq, dev_actual_clk_freq;
|
||||
uint32_t dev_actual_clk_src;
|
||||
int r;
|
||||
|
||||
/* Test clock_on(gating clock) */
|
||||
r = clock_control_on(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE),
|
||||
(clock_control_subsys_t) &pclken[0]);
|
||||
zassert_true((r == 0), "Could not enable ADC1 gating clock");
|
||||
|
||||
zassert_true(ADC_IS_CLK_ENABLED(), "ADC1 gating clock should be on");
|
||||
TC_PRINT("ADC1 gating clock on\n");
|
||||
|
||||
if (IS_ENABLED(STM32_ADC_DOMAIN_CLOCK_SUPPORT) && DT_NUM_CLOCKS(DT_NODELABEL(adc1)) > 1) {
|
||||
/* Test clock_on(domain_clk) */
|
||||
r = clock_control_configure(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE),
|
||||
(clock_control_subsys_t) &pclken[1],
|
||||
NULL);
|
||||
zassert_true((r == 0), "Could not enable ADC1 domain clock");
|
||||
TC_PRINT("ADC1 source clock configured\n");
|
||||
|
||||
/* Test clock source */
|
||||
zassert_true((ADC_SOURCE_PLL != -1), "Invalid ADC_SOURCE_PLL defined for target.");
|
||||
dev_actual_clk_src = GET_ADC_SOURCE();
|
||||
|
||||
switch (pclken[1].bus) {
|
||||
#if defined(STM32_SRC_PLL_P)
|
||||
case STM32_SRC_PLL_P:
|
||||
zassert_equal(dev_actual_clk_src, ADC_SOURCE_PLL,
|
||||
"Expected ADC1 src: PLL (0x%lx). Actual ADC1 src: 0x%x",
|
||||
ADC_SOURCE_PLL, dev_actual_clk_src);
|
||||
break;
|
||||
#endif
|
||||
default:
|
||||
zassert_true(0, "Unexpected src clk (%d)", dev_actual_clk_src);
|
||||
}
|
||||
|
||||
/* Test get_rate(srce clk) */
|
||||
r = clock_control_get_rate(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE),
|
||||
(clock_control_subsys_t) &pclken[1],
|
||||
&dev_dt_clk_freq);
|
||||
zassert_true((r == 0), "Could not get ADC1 clk srce freq");
|
||||
|
||||
dev_actual_clk_freq = HAL_RCCEx_GetPeriphCLKFreq(PERIPHCLK_ADC);
|
||||
zassert_equal(dev_dt_clk_freq, dev_actual_clk_freq,
|
||||
"Expected DT freq: %d Hz. Actual freq: %d Hz",
|
||||
dev_dt_clk_freq, dev_actual_clk_freq);
|
||||
|
||||
TC_PRINT("ADC1 clock source rate: %d Hz\n", dev_dt_clk_freq);
|
||||
} else {
|
||||
zassert_true((DT_NUM_CLOCKS(DT_NODELABEL(adc1)) == 1), "test config issue");
|
||||
/* No domain clock available, don't check gating clock as for adc there is no
|
||||
* uniform way to verify via hal.
|
||||
*/
|
||||
TC_PRINT("ADC1 no domain clock defined. Skipped check\n");
|
||||
}
|
||||
|
||||
/* Test clock_off(reg_clk) */
|
||||
r = clock_control_off(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE),
|
||||
(clock_control_subsys_t) &pclken[0]);
|
||||
zassert_true((r == 0), "Could not disable ADC1 gating clk");
|
||||
|
||||
zassert_true(!ADC_IS_CLK_ENABLED(), "ADC1 gating clk should be off");
|
||||
TC_PRINT("ADC1 gating clk off\n");
|
||||
|
||||
/* Test clock_off(domain clk) */
|
||||
/* Not supported today */
|
||||
}
|
||||
#endif
|
||||
|
|
@ -0,0 +1,121 @@
|
|||
/*
|
||||
* Copyright (c) 2022 Linaro Limited
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <zephyr/ztest.h>
|
||||
#include <soc.h>
|
||||
#include <zephyr/drivers/clock_control.h>
|
||||
#include <zephyr/drivers/clock_control/stm32_clock_control.h>
|
||||
#include <zephyr/logging/log.h>
|
||||
|
||||
#if !defined(CONFIG_SOC_SERIES_STM32F4X)
|
||||
#if DT_NODE_HAS_STATUS(DT_NODELABEL(i2c1), okay)
|
||||
|
||||
#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32_i2c_v1)
|
||||
#define DT_DRV_COMPAT st_stm32_i2c_v1
|
||||
#elif DT_HAS_COMPAT_STATUS_OKAY(st_stm32_i2c_v2)
|
||||
#define DT_DRV_COMPAT st_stm32_i2c_v2
|
||||
#endif
|
||||
|
||||
#if STM32_DT_INST_DEV_DOMAIN_CLOCK_SUPPORT
|
||||
#define STM32_I2C_DOMAIN_CLOCK_SUPPORT 1
|
||||
#else
|
||||
#define STM32_I2C_DOMAIN_CLOCK_SUPPORT 0
|
||||
#endif
|
||||
|
||||
static void i2c_set_clock(const struct stm32_pclken *clk)
|
||||
{
|
||||
uint32_t dev_dt_clk_freq, dev_actual_clk_freq;
|
||||
|
||||
/* Test clock_on(domain_clk) */
|
||||
int r = clock_control_configure(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE),
|
||||
(clock_control_subsys_t) clk,
|
||||
NULL);
|
||||
zassert_true((r == 0), "Could not enable I2C domain clock");
|
||||
TC_PRINT("I2C1 domain clock configured\n");
|
||||
|
||||
/* Test clock source */
|
||||
uint32_t dev_actual_clk_src = __HAL_RCC_GET_I2C1_SOURCE();
|
||||
|
||||
if (clk->bus == STM32_SRC_HSI) {
|
||||
zassert_equal(dev_actual_clk_src, RCC_I2C1CLKSOURCE_HSI,
|
||||
"Expected I2C src: HSI (0x%lx). Actual I2C src: 0x%x",
|
||||
RCC_I2C1CLKSOURCE_HSI, dev_actual_clk_src);
|
||||
} else if (clk->bus == STM32_SRC_SYSCLK) {
|
||||
zassert_equal(dev_actual_clk_src, RCC_I2C1CLKSOURCE_SYSCLK,
|
||||
"Expected I2C src: SYSCLK (0x%lx). Actual I2C src: 0x%x",
|
||||
RCC_I2C1CLKSOURCE_SYSCLK, dev_actual_clk_src);
|
||||
} else {
|
||||
zassert_true(0, "Unexpected domain clk (0x%x)", dev_actual_clk_src);
|
||||
}
|
||||
|
||||
/* Test get_rate(srce clk) */
|
||||
r = clock_control_get_rate(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE),
|
||||
(clock_control_subsys_t) clk,
|
||||
&dev_dt_clk_freq);
|
||||
zassert_true((r == 0), "Could not get I2C clk srce freq");
|
||||
|
||||
dev_actual_clk_freq = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_I2C1);
|
||||
zassert_equal(dev_dt_clk_freq, dev_actual_clk_freq,
|
||||
"Expected freq: %d Hz. Actual clk: %d Hz",
|
||||
dev_dt_clk_freq, dev_actual_clk_freq);
|
||||
|
||||
TC_PRINT("I2C1 clock source rate: %d Hz\n", dev_dt_clk_freq);
|
||||
}
|
||||
|
||||
ZTEST(stm32_common_devices_clocks, test_i2c_clk_config)
|
||||
{
|
||||
static const struct stm32_pclken pclken[] = STM32_DT_CLOCKS(DT_NODELABEL(i2c1));
|
||||
|
||||
uint32_t dev_dt_clk_freq, dev_actual_clk_freq;
|
||||
int r;
|
||||
|
||||
/* Test clock_on(gating clock) */
|
||||
r = clock_control_on(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE),
|
||||
(clock_control_subsys_t) &pclken[0]);
|
||||
zassert_true((r == 0), "Could not enable I2C gating clock");
|
||||
|
||||
zassert_true(__HAL_RCC_I2C1_IS_CLK_ENABLED(), "I2C1 gating clock should be on");
|
||||
TC_PRINT("I2C1 gating clock on\n");
|
||||
|
||||
if (IS_ENABLED(STM32_I2C_DOMAIN_CLOCK_SUPPORT) && DT_NUM_CLOCKS(DT_NODELABEL(i2c1)) > 1) {
|
||||
if (DT_NUM_CLOCKS(DT_NODELABEL(i2c1)) > 2) {
|
||||
/* set a dummy clock first, to check if the register is set correctly even
|
||||
* if not in reset state
|
||||
*/
|
||||
i2c_set_clock(&pclken[2]);
|
||||
}
|
||||
i2c_set_clock(&pclken[1]);
|
||||
} else {
|
||||
zassert_true((DT_NUM_CLOCKS(DT_NODELABEL(i2c1)) == 1), "test config issue");
|
||||
/* No domain clock available, get rate from gating clock */
|
||||
|
||||
/* Test get_rate */
|
||||
r = clock_control_get_rate(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE),
|
||||
(clock_control_subsys_t) &pclken[0],
|
||||
&dev_dt_clk_freq);
|
||||
zassert_true((r == 0), "Could not get I2C clk freq");
|
||||
|
||||
dev_actual_clk_freq = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_I2C1);
|
||||
zassert_equal(dev_dt_clk_freq, dev_actual_clk_freq,
|
||||
"Expected freq: %d Hz. Actual freq: %d Hz",
|
||||
dev_dt_clk_freq, dev_actual_clk_freq);
|
||||
|
||||
TC_PRINT("I2C1 clock source rate: %d Hz\n", dev_dt_clk_freq);
|
||||
}
|
||||
|
||||
/* Test clock_off(gating clk) */
|
||||
r = clock_control_off(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE),
|
||||
(clock_control_subsys_t) &pclken[0]);
|
||||
zassert_true((r == 0), "Could not disable I2C gating clk");
|
||||
|
||||
zassert_true(!__HAL_RCC_I2C1_IS_CLK_ENABLED(), "I2C1 gating clk should be off");
|
||||
TC_PRINT("I2C1 gating clk off\n");
|
||||
|
||||
/* Test clock_off(srce) */
|
||||
/* Not supported today */
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
|
|
@ -0,0 +1,104 @@
|
|||
/*
|
||||
* Copyright (c) 2022 Linaro Limited
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <zephyr/ztest.h>
|
||||
#include <soc.h>
|
||||
#include <zephyr/drivers/clock_control.h>
|
||||
#include <zephyr/drivers/clock_control/stm32_clock_control.h>
|
||||
#include <zephyr/logging/log.h>
|
||||
|
||||
#if DT_NODE_HAS_STATUS(DT_NODELABEL(lptim1), okay)
|
||||
|
||||
#undef DT_DRV_COMPAT
|
||||
#define DT_DRV_COMPAT st_stm32_lptim
|
||||
|
||||
#if STM32_DT_INST_DEV_DOMAIN_CLOCK_SUPPORT
|
||||
#define STM32_LPTIM_OPT_CLOCK_SUPPORT 1
|
||||
#else
|
||||
#define STM32_LPTIM_OPT_CLOCK_SUPPORT 0
|
||||
#endif
|
||||
|
||||
ZTEST(stm32_common_devices_clocks, test_lptim_clk_config)
|
||||
{
|
||||
static const struct stm32_pclken pclken[] = STM32_DT_CLOCKS(DT_NODELABEL(lptim1));
|
||||
|
||||
uint32_t dev_dt_clk_freq, dev_actual_clk_freq;
|
||||
uint32_t dev_actual_clk_src;
|
||||
int r;
|
||||
|
||||
/* Test clock_on(gating clock) */
|
||||
r = clock_control_on(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE),
|
||||
(clock_control_subsys_t) &pclken[0]);
|
||||
zassert_true((r == 0), "Could not enable LPTIM gating clock");
|
||||
|
||||
zassert_true(__HAL_RCC_LPTIM1_IS_CLK_ENABLED(), "LPTIM1 gating clock should be on");
|
||||
TC_PRINT("LPTIM1 gating clock on\n");
|
||||
|
||||
if (IS_ENABLED(STM32_LPTIM_OPT_CLOCK_SUPPORT) && DT_NUM_CLOCKS(DT_NODELABEL(lptim1)) > 1) {
|
||||
/* Test clock_on(domain_clk) */
|
||||
r = clock_control_configure(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE),
|
||||
(clock_control_subsys_t) &pclken[1],
|
||||
NULL);
|
||||
zassert_true((r == 0), "Could not enable LPTIM1 domain clock");
|
||||
TC_PRINT("LPTIM1 source clock configured\n");
|
||||
|
||||
/* Test clock source */
|
||||
dev_actual_clk_src = __HAL_RCC_GET_LPTIM1_SOURCE();
|
||||
|
||||
if (pclken[1].bus == STM32_SRC_LSE) {
|
||||
zassert_equal(dev_actual_clk_src, RCC_LPTIM1CLKSOURCE_LSE,
|
||||
"Expected LPTIM1 src: LSE (0x%lx). Actual LPTIM1 src: 0x%x",
|
||||
RCC_LPTIM1CLKSOURCE_LSE, dev_actual_clk_src);
|
||||
} else if (pclken[1].bus == STM32_SRC_LSI) {
|
||||
zassert_equal(dev_actual_clk_src, RCC_LPTIM1CLKSOURCE_LSI,
|
||||
"Expected LPTIM1 src: LSI (0x%lx). Actual LPTIM1 src: 0x%x",
|
||||
RCC_LPTIM1CLKSOURCE_LSI, dev_actual_clk_src);
|
||||
} else {
|
||||
zassert_true(0, "Unexpected domain clk (%d)", dev_actual_clk_src);
|
||||
}
|
||||
|
||||
/* Test get_rate(srce clk) */
|
||||
r = clock_control_get_rate(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE),
|
||||
(clock_control_subsys_t) &pclken[1],
|
||||
&dev_dt_clk_freq);
|
||||
zassert_true((r == 0), "Could not get LPTIM1 clk srce freq");
|
||||
|
||||
dev_actual_clk_freq = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_LPTIM1);
|
||||
zassert_equal(dev_dt_clk_freq, dev_actual_clk_freq,
|
||||
"Expected DT freq: %d Hz. Actual freq: %d Hz",
|
||||
dev_dt_clk_freq, dev_actual_clk_freq);
|
||||
|
||||
TC_PRINT("LPTIM1 clock source rate: %d Hz\n", dev_dt_clk_freq);
|
||||
} else {
|
||||
zassert_true((DT_NUM_CLOCKS(DT_NODELABEL(lptim1)) == 1), "test config issue");
|
||||
/* No domain clock available, get rate from gating clock */
|
||||
|
||||
/* Test get_rate */
|
||||
r = clock_control_get_rate(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE),
|
||||
(clock_control_subsys_t) &pclken[0],
|
||||
&dev_dt_clk_freq);
|
||||
zassert_true((r == 0), "Could not get LPTIM1 clk freq");
|
||||
|
||||
dev_actual_clk_freq = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_LPTIM1);
|
||||
zassert_equal(dev_dt_clk_freq, dev_actual_clk_freq,
|
||||
"Expected DT freq: %d Hz. Actual freq: %d Hz",
|
||||
dev_dt_clk_freq, dev_actual_clk_freq);
|
||||
|
||||
TC_PRINT("LPTIM1 clock source rate: %d Hz\n", dev_dt_clk_freq);
|
||||
}
|
||||
|
||||
/* Test clock_off(reg_clk) */
|
||||
r = clock_control_off(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE),
|
||||
(clock_control_subsys_t) &pclken[0]);
|
||||
zassert_true((r == 0), "Could not disable LPTIM1 gating clk");
|
||||
|
||||
zassert_true(!__HAL_RCC_LPTIM1_IS_CLK_ENABLED(), "LPTIM1 gating clk should be off");
|
||||
TC_PRINT("LPTIM1 gating clk off\n");
|
||||
|
||||
/* Test clock_off(domain clk) */
|
||||
/* Not supported today */
|
||||
}
|
||||
#endif
|
||||
Loading…
Add table
Add a link
Reference in a new issue