michaelh/zephyr
1
0
Fork 0
Code Releases Activity

drivers: dmic: update dmic flow initialization

Browse source 
DMIC configuration should allow the use of periodic start.

Signed-off-by: Damian Nikodem <damian.nikodem@intel.com>
This commit is contained in:
Damian Nikodem 2022-09-23 09:13:35 +02:00 • committed by Carles Cufí
commit 39c2007b04
2 changed files with 20 additions and 10 deletions
Download patch file Download diff file Expand all files Collapse all files

6
drivers/dai/intel/dmic/dmic.h
View file

@ -305,15 +305,18 @@
/* FIR_CONTROL_A bits */ /* FIR_CONTROL_A bits */
#define FIR_CONTROL_A_START_BIT BIT(7) #define FIR_CONTROL_A_START_BIT BIT(7)
#define FIR_CONTROL_A_ARRAY_START_EN_BIT BIT(6) #define FIR_CONTROL_A_ARRAY_START_EN_BIT BIT(6)
#define FIR_CONTROL_A_PERIODIC_START_EN_BIT BIT(5)
#define FIR_CONTROL_A_MUTE_BIT BIT(1) #define FIR_CONTROL_A_MUTE_BIT BIT(1)
#define FIR_CONTROL_A_START(x) SET_BIT(7, x) #define FIR_CONTROL_A_START(x) SET_BIT(7, x)
#define FIR_CONTROL_A_ARRAY_START_EN(x) SET_BIT(6, x) #define FIR_CONTROL_A_ARRAY_START_EN(x) SET_BIT(6, x)
#define FIR_CONTROL_A_PERIODIC_START_EN(x) SET_BIT(5, x)
#define FIR_CONTROL_A_DCCOMP(x) SET_BIT(4, x) #define FIR_CONTROL_A_DCCOMP(x) SET_BIT(4, x)
#define FIR_CONTROL_A_MUTE(x) SET_BIT(1, x) #define FIR_CONTROL_A_MUTE(x) SET_BIT(1, x)
#define FIR_CONTROL_A_STEREO(x) SET_BIT(0, x) #define FIR_CONTROL_A_STEREO(x) SET_BIT(0, x)
#define FIR_CONTROL_A_START_GET(x) GET_BIT(7, x) #define FIR_CONTROL_A_START_GET(x) GET_BIT(7, x)
#define FIR_CONTROL_A_ARRAY_START_EN_GET(x) GET_BIT(6, x) #define FIR_CONTROL_A_ARRAY_START_EN_GET(x) GET_BIT(6, x)
#define FIR_CONTROL_A_PERIODIC_START_EN_GET(x) GET_BIT(5, x)
#define FIR_CONTROL_A_DCCOMP_GET(x) GET_BIT(4, x) #define FIR_CONTROL_A_DCCOMP_GET(x) GET_BIT(4, x)
#define FIR_CONTROL_A_MUTE_GET(x) GET_BIT(1, x) #define FIR_CONTROL_A_MUTE_GET(x) GET_BIT(1, x)
#define FIR_CONTROL_A_STEREO_GET(x) GET_BIT(0, x) #define FIR_CONTROL_A_STEREO_GET(x) GET_BIT(0, x)
@ -352,15 +355,18 @@
/* FIR_CONTROL_B bits */ /* FIR_CONTROL_B bits */
#define FIR_CONTROL_B_START_BIT BIT(7) #define FIR_CONTROL_B_START_BIT BIT(7)
#define FIR_CONTROL_B_ARRAY_START_EN_BIT BIT(6) #define FIR_CONTROL_B_ARRAY_START_EN_BIT BIT(6)
#define FIR_CONTROL_B_PERIODIC_START_EN_BIT BIT(5)
#define FIR_CONTROL_B_MUTE_BIT BIT(1) #define FIR_CONTROL_B_MUTE_BIT BIT(1)
#define FIR_CONTROL_B_START(x) SET_BIT(7, x) #define FIR_CONTROL_B_START(x) SET_BIT(7, x)
#define FIR_CONTROL_B_ARRAY_START_EN(x) SET_BIT(6, x) #define FIR_CONTROL_B_ARRAY_START_EN(x) SET_BIT(6, x)
#define FIR_CONTROL_B_PERIODIC_START_EN(x) SET_BIT(5, x)
#define FIR_CONTROL_B_DCCOMP(x) SET_BIT(4, x) #define FIR_CONTROL_B_DCCOMP(x) SET_BIT(4, x)
#define FIR_CONTROL_B_MUTE(x) SET_BIT(1, x) #define FIR_CONTROL_B_MUTE(x) SET_BIT(1, x)
#define FIR_CONTROL_B_STEREO(x) SET_BIT(0, x) #define FIR_CONTROL_B_STEREO(x) SET_BIT(0, x)
#define FIR_CONTROL_B_START_GET(x) GET_BIT(7, x) #define FIR_CONTROL_B_START_GET(x) GET_BIT(7, x)
#define FIR_CONTROL_B_ARRAY_START_EN_GET(x) GET_BIT(6, x) #define FIR_CONTROL_B_ARRAY_START_EN_GET(x) GET_BIT(6, x)
#define FIR_CONTROL_B_PERIODIC_START_EN_GET(x) GET_BIT(5, x)
#define FIR_CONTROL_B_DCCOMP_GET(x) GET_BIT(4, x) #define FIR_CONTROL_B_DCCOMP_GET(x) GET_BIT(4, x)
#define FIR_CONTROL_B_MUTE_GET(x) GET_BIT(1, x) #define FIR_CONTROL_B_MUTE_GET(x) GET_BIT(1, x)
#define FIR_CONTROL_B_STEREO_GET(x) GET_BIT(0, x) #define FIR_CONTROL_B_STEREO_GET(x) GET_BIT(0, x)

24
drivers/dai/intel/dmic/dmic_nhlt.c
View file

@ -436,15 +436,17 @@ int dai_dmic_set_config_nhlt(struct dai_intel_dmic *dmic, const void *bespoke_cf
val = fir_cfg_a[n]->fir_control; val = fir_cfg_a[n]->fir_control;
bf1 = FIR_CONTROL_A_START_GET(val); bf1 = FIR_CONTROL_A_START_GET(val);
bf2 = FIR_CONTROL_A_ARRAY_START_EN_GET(val); bf2 = FIR_CONTROL_A_ARRAY_START_EN_GET(val);
bf3 = FIR_CONTROL_A_DCCOMP_GET(val); bf3 = FIR_CONTROL_A_PERIODIC_START_EN_GET(val);
bf4 = FIR_CONTROL_A_MUTE_GET(val); bf4 = FIR_CONTROL_A_DCCOMP_GET(val);
bf5 = FIR_CONTROL_A_STEREO_GET(val); bf5 = FIR_CONTROL_A_MUTE_GET(val);
bf6 = FIR_CONTROL_A_STEREO_GET(val);
LOG_DBG("dmic_set_config_nhlt(): FIR_CONTROL_A = %08x", val); LOG_DBG("dmic_set_config_nhlt(): FIR_CONTROL_A = %08x", val);
LOG_DBG(" start=%d, array_start_en=%d, dccomp=%d", bf1, bf2, bf3); LOG_DBG(" start=%d, array_start_en=%d, periodic_start_en=%d",
LOG_DBG(" mute=%d, stereo=%d", bf4, bf5); bf1, bf2, bf3);
LOG_DBG(" dccomp=%d, mute=%d, stereo=%d", bf4, bf5, bf6);
ref = FIR_CONTROL_A_START(bf1) | FIR_CONTROL_A_ARRAY_START_EN(bf2) | ref = FIR_CONTROL_A_START(bf1) | FIR_CONTROL_A_ARRAY_START_EN(bf2) |
FIR_CONTROL_A_DCCOMP(bf3) | FIR_CONTROL_A_MUTE(bf4) | FIR_CONTROL_A_PERIODIC_START_EN(bf3) | FIR_CONTROL_A_DCCOMP(bf4) |
FIR_CONTROL_A_STEREO(bf5); FIR_CONTROL_A_MUTE(bf5) | FIR_CONTROL_A_STEREO(bf6);
if (ref != val) { if (ref != val) {
LOG_ERR("dmic_set_config_nhlt(): illegal FIR_CONTROL = 0x%08x", LOG_ERR("dmic_set_config_nhlt(): illegal FIR_CONTROL = 0x%08x",
@ -496,12 +498,14 @@ int dai_dmic_set_config_nhlt(struct dai_intel_dmic *dmic, const void *bespoke_cf
val = fir_cfg_b[n]->fir_control; val = fir_cfg_b[n]->fir_control;
bf1 = FIR_CONTROL_B_START_GET(val); bf1 = FIR_CONTROL_B_START_GET(val);
bf2 = FIR_CONTROL_B_ARRAY_START_EN_GET(val); bf2 = FIR_CONTROL_B_ARRAY_START_EN_GET(val);
bf3 = FIR_CONTROL_B_DCCOMP_GET(val); bf3 = FIR_CONTROL_B_PERIODIC_START_EN_GET(val);
bf4 = FIR_CONTROL_B_DCCOMP_GET(val);
bf5 = FIR_CONTROL_B_MUTE_GET(val); bf5 = FIR_CONTROL_B_MUTE_GET(val);
bf6 = FIR_CONTROL_B_STEREO_GET(val); bf6 = FIR_CONTROL_B_STEREO_GET(val);
LOG_DBG("dmic_set_config_nhlt(): FIR_CONTROL_B = %08x", val); LOG_DBG("dmic_set_config_nhlt(): FIR_CONTROL_B = %08x", val);
LOG_DBG(" start=%d, array_start_en=%d, dccomp=%d", bf1, bf2, bf3); LOG_DBG(" start=%d, array_start_en=%d, periodic_start_en=%d",
LOG_DBG(" mute=%d, stereo=%d", bf5, bf6); bf1, bf2, bf3);
LOG_DBG(" dccomp=%d, mute=%d, stereo=%d", bf4, bf5, bf6);
/* Clear START, set MUTE */ /* Clear START, set MUTE */
fir_control = (val & ~FIR_CONTROL_B_START_BIT) | FIR_CONTROL_B_MUTE_BIT; fir_control = (val & ~FIR_CONTROL_B_START_BIT) | FIR_CONTROL_B_MUTE_BIT;