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drivers: i2c: stm32: add support for H7 series

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Enable I2C driver for STM32 H7 series.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
This commit is contained in:
Gerard Marull-Paretas 2020-03-06 17:35:32 +01:00 • committed by Maureen Helm
commit 39b1f6cbba
6 changed files with 172 additions and 4 deletions
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9
drivers/i2c/Kconfig.stm32
View file

@ -20,13 +20,16 @@ config I2C_STM32_V1
config I2C_STM32_V2
bool
depends on SOC_SERIES_STM32F0X || SOC_SERIES_STM32F3X || SOC_SERIES_STM32F7X || SOC_SERIES_STM32L0X || SOC_SERIES_STM32L4X || SOC_SERIES_STM32WBX || SOC_SERIES_STM32MP1X || SOC_SERIES_STM32G0X || SOC_SERIES_STM32G4X
depends on (SOC_SERIES_STM32F0X || SOC_SERIES_STM32F3X || \
SOC_SERIES_STM32F7X || SOC_SERIES_STM32L0X || SOC_SERIES_STM32L4X || \
SOC_SERIES_STM32WBX || SOC_SERIES_STM32MP1X || SOC_SERIES_STM32G0X || \
SOC_SERIES_STM32G4X || SOC_SERIES_STM32H7X)
select USE_STM32_LL_I2C
select USE_STM32_LL_RCC if SOC_SERIES_STM32F0X || SOC_SERIES_STM32F3X
select I2C_STM32_INTERRUPT if I2C_SLAVE
help
Enable I2C support on the STM32 F0, F3, F7, L4, WBX, MP1, G0 and G4 family of
processors.
Enable I2C support on the STM32 F0, F3, F7, L4, WBX, MP1, G0, G4 and
H7 family of processors.
This driver also supports the L0 series.
If I2C_SLAVE is enabled it selects I2C_STM32_INTERRUPT, since slave mode
is only supported by this driver with interrupts enabled.

65
drivers/pinmux/stm32/pinmux_stm32h7.h
View file

@ -1,5 +1,6 @@
/*
* Copyright (c) 2019 Linaro Limited
* Copyright (c) 2020 Teslabs Engineering S.L.
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -28,6 +29,9 @@
#define STM32H7_PINMUX_FUNC_PA3_USART2_RX \
(STM32_PINMUX_ALT_FUNC_7 | STM32_PUSHPULL_NOPULL)
#define STM32H7_PINMUX_FUNC_PA8_I2C3_SCL \
(STM32_PINMUX_ALT_FUNC_4 | STM32_OPENDRAIN_PULLUP)
#define STM32H7_PINMUX_FUNC_PA9_USART1_TX \
(STM32_PINMUX_ALT_FUNC_7 | STM32_PUSHPULL_PULLUP)
#define STM32H7_PINMUX_FUNC_PA9_SPI2_SCK \
@ -50,19 +54,41 @@
(STM32_PINMUX_ALT_FUNC_8 | STM32_PUSHPULL_PULLUP)
/* Port B */
#define STM32H7_PINMUX_FUNC_PB6_I2C1_SCL \
(STM32_PINMUX_ALT_FUNC_4 | STM32_OPENDRAIN_PULLUP)
#define STM32H7_PINMUX_FUNC_PB6_I2C4_SCL \
(STM32_PINMUX_ALT_FUNC_6 | STM32_OPENDRAIN_PULLUP)
#define STM32H7_PINMUX_FUNC_PB6_USART1_TX \
(STM32_PINMUX_ALT_FUNC_7 | STM32_PUSHPULL_PULLUP)
#define STM32H7_PINMUX_FUNC_PB6_LPUART1_TX \
(STM32_PINMUX_ALT_FUNC_8 | STM32_OPENDRAIN_PULLUP)
#define STM32H7_PINMUX_FUNC_PB7_I2C1_SDA \
(STM32_PINMUX_ALT_FUNC_4 | STM32_OPENDRAIN_PULLUP)
#define STM32H7_PINMUX_FUNC_PB7_I2C4_SDA \
(STM32_PINMUX_ALT_FUNC_6 | STM32_OPENDRAIN_PULLUP)
#define STM32H7_PINMUX_FUNC_PB7_USART1_RX \
(STM32_PINMUX_ALT_FUNC_7 | STM32_PUSHPULL_NOPULL)
#define STM32H7_PINMUX_FUNC_PB7_LPUART1_RX \
(STM32_PINMUX_ALT_FUNC_8 | STM32_PUSHPULL_NOPULL)
#define STM32H7_PINMUX_FUNC_PB8_I2C1_SCL \
(STM32_PINMUX_ALT_FUNC_4 | STM32_OPENDRAIN_PULLUP)
#define STM32H7_PINMUX_FUNC_PB8_I2C4_SCL \
(STM32_PINMUX_ALT_FUNC_6 | STM32_OPENDRAIN_PULLUP)
#define STM32H7_PINMUX_FUNC_PB9_I2C1_SDA \
(STM32_PINMUX_ALT_FUNC_4 | STM32_OPENDRAIN_PULLUP)
#define STM32H7_PINMUX_FUNC_PB9_I2C4_SDA \
(STM32_PINMUX_ALT_FUNC_6 | STM32_OPENDRAIN_PULLUP)
#define STM32H7_PINMUX_FUNC_PB10_I2C2_SCL \
(STM32_PINMUX_ALT_FUNC_4 | STM32_OPENDRAIN_PULLUP)
#define STM32H7_PINMUX_FUNC_PB10_USART3_TX \
(STM32_PINMUX_ALT_FUNC_7 | STM32_PUSHPULL_PULLUP)
#define STM32H7_PINMUX_FUNC_PB11_I2C2_SDA \
(STM32_PINMUX_ALT_FUNC_4 | STM32_OPENDRAIN_PULLUP)
#define STM32H7_PINMUX_FUNC_PB11_USART3_RX \
(STM32_PINMUX_ALT_FUNC_7 | STM32_PUSHPULL_NOPULL)
@ -79,6 +105,8 @@
#define STM32H7_PINMUX_FUNC_PC8_UART5_RTS \
(STM32_PINMUX_ALT_FUNC_7 | STM32_PUSHPULL_PULLUP)
#define STM32H7_PINMUX_FUNC_PC9_I2C3_SDA \
(STM32_PINMUX_ALT_FUNC_4 | STM32_OPENDRAIN_PULLUP)
#define STM32H7_PINMUX_FUNC_PC9_UART5_CTS \
(STM32_PINMUX_ALT_FUNC_7 | STM32_PUSHPULL_PULLUP)
@ -120,9 +148,14 @@
#define STM32H7_PINMUX_FUNC_PD11_USART3_CTS \
(STM32_PINMUX_ALT_FUNC_7 | STM32_PUSHPULL_PULLUP)
#define STM32H7_PINMUX_FUNC_PD12_I2C4_SCL \
(STM32_PINMUX_ALT_FUNC_4 | STM32_OPENDRAIN_PULLUP)
#define STM32H7_PINMUX_FUNC_PD12_USART3_RTS \
(STM32_PINMUX_ALT_FUNC_7 | STM32_PUSHPULL_PULLUP)
#define STM32H7_PINMUX_FUNC_PD13_I2C4_SDA \
(STM32_PINMUX_ALT_FUNC_4 | STM32_OPENDRAIN_PULLUP)
#define STM32H7_PINMUX_FUNC_PD14_UART8_CTS \
(STM32_PINMUX_ALT_FUNC_8 | STM32_PUSHPULL_PULLUP)
@ -150,6 +183,12 @@
/* Port F */
#define STM32H7_PINMUX_FUNC_PF0_I2C2_SDA \
(STM32_PINMUX_ALT_FUNC_4 | STM32_OPENDRAIN_PULLUP)
#define STM32H7_PINMUX_FUNC_PF1_I2C2_SCL \
(STM32_PINMUX_ALT_FUNC_4 | STM32_OPENDRAIN_PULLUP)
#define STM32H7_PINMUX_FUNC_PF6_UART7_RX \
(STM32_PINMUX_ALT_FUNC_8 | STM32_PUSHPULL_NOPULL)
@ -162,6 +201,13 @@
#define STM32H7_PINMUX_FUNC_PF9_UART7_CTS \
(STM32_PINMUX_ALT_FUNC_8 | STM32_PUSHPULL_PULLUP)
#define STM32H7_PINMUX_FUNC_PF14_I2C4_SCL \
(STM32_PINMUX_ALT_FUNC_4 | STM32_OPENDRAIN_PULLUP)
#define STM32H7_PINMUX_FUNC_PF15_I2C4_SDA \
(STM32_PINMUX_ALT_FUNC_4 | STM32_OPENDRAIN_PULLUP)
/* Port G */
#define STM32H7_PINMUX_FUNC_PG8_USART6_RTS \
(STM32_PINMUX_ALT_FUNC_8 | STM32_PUSHPULL_PULLUP)
@ -181,6 +227,23 @@
(STM32_PINMUX_ALT_FUNC_8 | STM32_PUSHPULL_PULLUP)
/* Port H */
#define STM32H7_PINMUX_FUNC_PH4_I2C2_SCL \
(STM32_PINMUX_ALT_FUNC_4 | STM32_OPENDRAIN_PULLUP)
#define STM32H7_PINMUX_FUNC_PH5_I2C2_SDA \
(STM32_PINMUX_ALT_FUNC_4 | STM32_OPENDRAIN_PULLUP)
#define STM32H7_PINMUX_FUNC_PH7_I2C3_SCL \
(STM32_PINMUX_ALT_FUNC_4 | STM32_OPENDRAIN_PULLUP)
#define STM32H7_PINMUX_FUNC_PH8_I2C3_SDA \
(STM32_PINMUX_ALT_FUNC_4 | STM32_OPENDRAIN_PULLUP)
#define STM32H7_PINMUX_FUNC_PH11_I2C4_SCL \
(STM32_PINMUX_ALT_FUNC_4 | STM32_OPENDRAIN_PULLUP)
#define STM32H7_PINMUX_FUNC_PH12_I2C4_SDA \
(STM32_PINMUX_ALT_FUNC_4 | STM32_OPENDRAIN_PULLUP)
/* Port I */
@ -193,4 +256,4 @@
/* Port K */
#endif /* ZEPHYR_DRIVERS_PINMUX_STM32_PINMUX_STM32F7_H_ */
#endif /* ZEPHYR_DRIVERS_PINMUX_STM32_PINMUX_STM32H7_H_ */

54
dts/arm/st/h7/stm32h7.dtsi
View file

@ -1,6 +1,7 @@
/*
* Copyright (c) 2019 Linaro Limited
* Copyright (c) 2019 Centaur Analytics, Inc
* Copyright (c) 2020 Teslabs Engineering S.L.
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -8,6 +9,7 @@
#include <arm/armv7-m.dtsi>
#include <dt-bindings/clock/stm32_clock.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/i2c/i2c.h>
/ {
cpus {
@ -236,6 +238,58 @@
status = "disabled";
label = "RTC_0";
};
i2c1: i2c@40005400 {
compatible = "st,stm32-i2c-v2";
clock-frequency = <I2C_BITRATE_STANDARD>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40005400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00200000>;
interrupts = <31 0>, <32 0>;
interrupt-names = "event", "error";
status = "disabled";
label = "I2C_1";
};
i2c2: i2c@40005800 {
compatible = "st,stm32-i2c-v2";
clock-frequency = <I2C_BITRATE_STANDARD>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40005800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00400000>;
interrupts = <33 0>, <34 0>;
interrupt-names = "event", "error";
status = "disabled";
label = "I2C_2";
};
i2c3: i2c@40005c00 {
compatible = "st,stm32-i2c-v2";
clock-frequency = <I2C_BITRATE_STANDARD>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40005c00 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00800000>;
interrupts = <72 0>, <73 0>;
interrupt-names = "event", "error";
status = "disabled";
label = "I2C_3";
};
i2c4: i2c@58001c00 {
compatible = "st,stm32-i2c-v2";
clock-frequency = <I2C_BITRATE_STANDARD>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x58001c00 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB4 0x00000080>;
interrupts = <95 0>, <96 0>;
interrupt-names = "event", "error";
status = "disabled";
label = "I2C_4";
};
};
};

4
soc/arm/st_stm32/stm32h7/Kconfig.defconfig.series
View file

@ -42,4 +42,8 @@ config GPIO_STM32_PORTK
endif # GPIO_STM32
config I2C_STM32_V2
default y
depends on I2C_STM32
endif # SOC_SERIES_STM32H7X

40
soc/arm/st_stm32/stm32h7/dts_fixup.h
View file

@ -111,4 +111,44 @@
#define DT_RTC_0_NAME DT_INST_0_ST_STM32_RTC_LABEL
#define DT_I2C_1_BASE_ADDRESS DT_ST_STM32_I2C_V2_40005400_BASE_ADDRESS
#define DT_I2C_1_EVENT_IRQ_PRI DT_ST_STM32_I2C_V2_40005400_IRQ_EVENT_PRIORITY
#define DT_I2C_1_ERROR_IRQ_PRI DT_ST_STM32_I2C_V2_40005400_IRQ_ERROR_PRIORITY
#define DT_I2C_1_NAME DT_ST_STM32_I2C_V2_40005400_LABEL
#define DT_I2C_1_EVENT_IRQ DT_ST_STM32_I2C_V2_40005400_IRQ_EVENT
#define DT_I2C_1_ERROR_IRQ DT_ST_STM32_I2C_V2_40005400_IRQ_ERROR
#define DT_I2C_1_BITRATE DT_ST_STM32_I2C_V2_40005400_CLOCK_FREQUENCY
#define DT_I2C_1_CLOCK_BITS DT_ST_STM32_I2C_V2_40005400_CLOCK_BITS
#define DT_I2C_1_CLOCK_BUS DT_ST_STM32_I2C_V2_40005400_CLOCK_BUS
#define DT_I2C_2_BASE_ADDRESS DT_ST_STM32_I2C_V2_40005800_BASE_ADDRESS
#define DT_I2C_2_EVENT_IRQ_PRI DT_ST_STM32_I2C_V2_40005800_IRQ_EVENT_PRIORITY
#define DT_I2C_2_ERROR_IRQ_PRI DT_ST_STM32_I2C_V2_40005800_IRQ_ERROR_PRIORITY
#define DT_I2C_2_NAME DT_ST_STM32_I2C_V2_40005800_LABEL
#define DT_I2C_2_EVENT_IRQ DT_ST_STM32_I2C_V2_40005800_IRQ_EVENT
#define DT_I2C_2_ERROR_IRQ DT_ST_STM32_I2C_V2_40005800_IRQ_ERROR
#define DT_I2C_2_BITRATE DT_ST_STM32_I2C_V2_40005800_CLOCK_FREQUENCY
#define DT_I2C_2_CLOCK_BITS DT_ST_STM32_I2C_V2_40005800_CLOCK_BITS
#define DT_I2C_2_CLOCK_BUS DT_ST_STM32_I2C_V2_40005800_CLOCK_BUS
#define DT_I2C_3_BASE_ADDRESS DT_ST_STM32_I2C_V2_40005C00_BASE_ADDRESS
#define DT_I2C_3_EVENT_IRQ_PRI DT_ST_STM32_I2C_V2_40005C00_IRQ_EVENT_PRIORITY
#define DT_I2C_3_ERROR_IRQ_PRI DT_ST_STM32_I2C_V2_40005C00_IRQ_ERROR_PRIORITY
#define DT_I2C_3_NAME DT_ST_STM32_I2C_V2_40005C00_LABEL
#define DT_I2C_3_EVENT_IRQ DT_ST_STM32_I2C_V2_40005C00_IRQ_EVENT
#define DT_I2C_3_ERROR_IRQ DT_ST_STM32_I2C_V2_40005C00_IRQ_ERROR
#define DT_I2C_3_BITRATE DT_ST_STM32_I2C_V2_40005C00_CLOCK_FREQUENCY
#define DT_I2C_3_CLOCK_BITS DT_ST_STM32_I2C_V2_40005C00_CLOCK_BITS
#define DT_I2C_3_CLOCK_BUS DT_ST_STM32_I2C_V2_40005C00_CLOCK_BUS
#define DT_I2C_4_BASE_ADDRESS DT_ST_STM32_I2C_V2_58001C00_BASE_ADDRESS
#define DT_I2C_4_EVENT_IRQ_PRI DT_ST_STM32_I2C_V2_58001C00_IRQ_EVENT_PRIORITY
#define DT_I2C_4_ERROR_IRQ_PRI DT_ST_STM32_I2C_V2_58001C00_IRQ_ERROR_PRIORITY
#define DT_I2C_4_NAME DT_ST_STM32_I2C_V2_58001C00_LABEL
#define DT_I2C_4_EVENT_IRQ DT_ST_STM32_I2C_V2_58001C00_IRQ_EVENT
#define DT_I2C_4_ERROR_IRQ DT_ST_STM32_I2C_V2_58001C00_IRQ_ERROR
#define DT_I2C_4_BITRATE DT_ST_STM32_I2C_V2_58001C00_CLOCK_FREQUENCY
#define DT_I2C_4_CLOCK_BITS DT_ST_STM32_I2C_V2_58001C00_CLOCK_BITS
#define DT_I2C_4_CLOCK_BUS DT_ST_STM32_I2C_V2_58001C00_CLOCK_BUS
/* End of SoC Level DTS fixup file */

4
soc/arm/st_stm32/stm32h7/soc.h
View file

@ -70,6 +70,10 @@
#include <stm32h7xx_ll_pwr.h>
#endif /* CONFIG_COUNTER_RTC_STM32 */
#ifdef CONFIG_I2C_STM32
#include <stm32h7xx_ll_i2c.h>
#endif /* CONFIG_I2C_STM32 */
#endif /* !_ASMLANGUAGE */
#endif /* _STM32F7_SOC_H7_ */