nxp: imx8ulp: enable pinctrl

This commit enables pinctrl on i.MX8ULP. This includes:
	1) Adding `pinctrl_soc.h` header file.
	2) Adding DTS node for IOMUXC1, which is one of the
	IPs responsible for managing the 8ULP pads.
	3) Adding .dtsi with pin definitions. For now, only
	the LPUART7 pads are added to this file because this
	is going to be the only consummer for now.
	4) Modifying the `pinctrl_imx.c` driver to work for 8ULP.
	5) Enabling the `CONFIG_HAS_MCUX_IOMUXC`, which is a
	dependency of `CONFIG_PINCTRL_IMX`.

Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>

boards/nxp/imx8ulp_evk/imx8ulp_evk_mimx8ud7_adsp-pinctrl.dtsi

@@ -0,0 +1,23 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&iomuxc1 {
+	iomuxc1_ptf22_lpuart7_tx: IOMUXC_PTF22_LPUART7_TX {
+		pinmux = <0x298c0158 0x4 0x298c09e0 0x3 0x298c0158>;
+	};
+
+	iomuxc1_ptf23_lpuart7_rx: IOMUXC_PTF23_LPUART7_RX {
+		pinmux = <0x298c015c 0x4 0x298c09dc 0x3 0x298c015c>;
+	};
+};
+
+&pinctrl {
+	lpuart7_default: lpuart7_default {
+		group0 {
+			pinmux = <&iomuxc1_ptf22_lpuart7_tx>, <&iomuxc1_ptf23_lpuart7_rx>;
+		};
+	};
+};

boards/nxp/imx8ulp_evk/imx8ulp_evk_mimx8ud7_adsp.dts

@@ -7,6 +7,7 @@
 /dts-v1/;
 
 #include <nxp/nxp_imx8ulp.dtsi>
+#include "imx8ulp_evk_mimx8ud7_adsp-pinctrl.dtsi"
 
 / {
 	model = "NXP i.MX 8ULP Audio DSP";

drivers/pinctrl/pinctrl_imx.c

@@ -45,6 +45,22 @@ int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt,
 			sys_write32(pin_ctrl_flags & (~(0x1 << MCUX_IMX_INPUT_ENABLE_SHIFT)),
 				    (mem_addr_t)config_register);
 		}
+#elif defined(CONFIG_SOC_MIMX8UD7)
+		if (mux_register == config_register) {
+			sys_write32(IOMUXC_PCR_MUX_MODE(mux_mode) |
+				    pin_ctrl_flags, (mem_addr_t)mux_register);
+		} else {
+			sys_write32(IOMUXC_PCR_MUX_MODE(mux_mode),
+				    (mem_addr_t)mux_register);
+
+			if (config_register) {
+				sys_write32(pin_ctrl_flags, (mem_addr_t)config_register);
+			}
+		}
+
+		if (input_register) {
+			sys_write32(IOMUXC_PSMI_SSS(input_daisy), (mem_addr_t)input_register);
+		}
 #else
 		sys_write32(
 			IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(mux_mode) |

dts/bindings/pinctrl/nxp,imx8ulp-pinctrl.yaml

@@ -0,0 +1,48 @@
+# Copyright 2024 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+description: Use this compatible for the i.MX8ULP boards
+
+compatible: "nxp,imx8ulp-pinctrl"
+
+include: base.yaml
+
+child-binding:
+  description: i.MX8ULP pin controller pin group
+  child-binding:
+    description: i.MX8ULP pin controller pin configuration node
+    include:
+      - name: pincfg-node.yaml
+        property-allowlist:
+          - bias-pull-up
+          - bias-pull-down
+          - drive-open-drain
+    properties:
+      pinmux:
+        required: true
+        type: phandles
+      drive-strength:
+        type: string
+        description: |
+          Used to configure the pad's drive strength, which, together
+          with the slew rate, affects the maximum frequency the pad's
+          output buffer can yield. If "normal" drive strength is used,
+          the maximum frequency will be lower as per the measurements
+          found in the SoC datasheet. Note that the TRM refers to the
+          "normal" drive strength as "standard". If unspecified, the
+          default will be "normal".
+        enum:
+          - "normal"
+          - "high"
+      slew-rate:
+        type: string
+        description: |
+          Used to configure the pad's slew rate, which affects the
+          maximum frequency the pad's output buffer can yield (
+          "fast" slew rate -> higher pad frequency, "slow" slew rate ->
+          lower pad frequency). Note that the TRM refers to the "fast"
+          slew rate as "standard". If unspecified, the default will be
+          "fast".
+        enum:
+          - "fast"
+          - "slow"

dts/xtensa/nxp/nxp_imx8ulp.dtsi

@@ -37,4 +37,12 @@
 		reg = <0x29800000 DT_SIZE_K(64)>;
 		#clock-cells = <2>;
 	};
+
+	iomuxc1: pinctrl@298c0000 {
+		compatible = "nxp,imx-iomuxc";
+		reg = <0x298c0000 DT_SIZE_K(64)>;
+		pinctrl: pinctrl {
+			compatible = "nxp,imx8ulp-pinctrl";
+		};
+	};
 };

soc/nxp/imx/imx8ulp/Kconfig

@@ -11,6 +11,7 @@ config SOC_MIMX8UD7_ADSP
 	select XTENSA_SMALL_VECTOR_TABLE_ENTRY
 	select CPU_HAS_DCACHE
 	select HAS_MCUX
+	select HAS_MCUX_IOMUXC
 
 # note: the NXP HAL refers to the HIFI4 DSP as
 # `dsp1` and the Fusion DSP as `dsp0`, thus the

soc/nxp/imx/imx8ulp/pinctrl_soc.h

@@ -0,0 +1,68 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_SOC_NXP_IMX_IMX8ULP_PINCTR_SOC_H_
+#define ZEPHYR_SOC_NXP_IMX_IMX8ULP_PINCTR_SOC_H_
+
+#include <zephyr/devicetree.h>
+#include "fsl_iomuxc.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct pinctrl_soc_pinmux {
+	uint32_t mux_register;
+	uint8_t mux_mode;
+	uint32_t input_register;
+	uint32_t input_daisy;
+	uint32_t config_register;
+};
+
+struct pinctrl_soc_pin {
+	struct pinctrl_soc_pinmux pinmux;
+	uint32_t pin_ctrl_flags;
+};
+
+typedef struct pinctrl_soc_pin pinctrl_soc_pin_t;
+
+#define _PULL_IS_ENABLED(node_id)\
+	(DT_PROP(node_id, bias_pull_up) || DT_PROP(node_id, bias_pull_down))
+
+#define _IMX8ULP_PIN_FLAGS(node_id)						\
+	((DT_ENUM_IDX_OR(node_id, drive_strength, 0) << IOMUXC_PCR_DSE_SHIFT) |	\
+	 (DT_PROP(node_id, drive_open_drain) << IOMUXC_PCR_ODE_SHIFT) |		\
+	 (DT_ENUM_IDX_OR(node_id, slew_rate, 0) << IOMUXC_PCR_SRE_SHIFT) |	\
+	 (DT_PROP(node_id, bias_pull_up) << IOMUXC_PCR_PS_SHIFT) |		\
+	 (_PULL_IS_ENABLED(node_id) << IOMUXC_PCR_PE_SHIFT))
+
+#define _IMX8ULP_PINMUX(node_id)					\
+	{								\
+		.mux_register = DT_PROP_BY_IDX(node_id, pinmux, 0),	\
+		.config_register = DT_PROP_BY_IDX(node_id, pinmux, 4),	\
+		.input_register = DT_PROP_BY_IDX(node_id, pinmux, 2),	\
+		.mux_mode = DT_PROP_BY_IDX(node_id, pinmux, 1),		\
+		.input_daisy = DT_PROP_BY_IDX(node_id, pinmux, 3),	\
+	}
+
+#define Z_PINCTRL_PINMUX(group_id, pin_prop, idx)\
+	_IMX8ULP_PINMUX(DT_PHANDLE_BY_IDX(group_id, pin_prop, idx))
+
+#define Z_PINCTRL_STATE_PIN_INIT(group_id, pin_prop, idx)		\
+	{								\
+		.pinmux = Z_PINCTRL_PINMUX(group_id, pin_prop, idx),	\
+		.pin_ctrl_flags = _IMX8ULP_PIN_FLAGS(group_id),		\
+	},
+
+#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop)\
+	{ DT_FOREACH_CHILD_VARGS(DT_PHANDLE(node_id, prop),\
+				 DT_FOREACH_PROP_ELEM, pinmux, Z_PINCTRL_STATE_PIN_INIT) };
+
+#ifdef __cplusplus
+{
+#endif
+
+#endif /* ZEPHYR_SOC_NXP_IMX_IMX8ULP_PINCTR_SOC_H_ */