nxp: imx8ulp: enable pinctrl

This commit enables pinctrl on i.MX8ULP. This includes:
	1) Adding `pinctrl_soc.h` header file.
	2) Adding DTS node for IOMUXC1, which is one of the
	IPs responsible for managing the 8ULP pads.
	3) Adding .dtsi with pin definitions. For now, only
	the LPUART7 pads are added to this file because this
	is going to be the only consummer for now.
	4) Modifying the `pinctrl_imx.c` driver to work for 8ULP.
	5) Enabling the `CONFIG_HAS_MCUX_IOMUXC`, which is a
	dependency of `CONFIG_PINCTRL_IMX`.

Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
This commit is contained in:
Laurentiu Mihalcea 2024-03-21 15:35:49 +02:00 committed by Carles Cufí
commit 399c2cba65
7 changed files with 165 additions and 0 deletions

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# Copyright 2024 NXP
# SPDX-License-Identifier: Apache-2.0
description: Use this compatible for the i.MX8ULP boards
compatible: "nxp,imx8ulp-pinctrl"
include: base.yaml
child-binding:
description: i.MX8ULP pin controller pin group
child-binding:
description: i.MX8ULP pin controller pin configuration node
include:
- name: pincfg-node.yaml
property-allowlist:
- bias-pull-up
- bias-pull-down
- drive-open-drain
properties:
pinmux:
required: true
type: phandles
drive-strength:
type: string
description: |
Used to configure the pad's drive strength, which, together
with the slew rate, affects the maximum frequency the pad's
output buffer can yield. If "normal" drive strength is used,
the maximum frequency will be lower as per the measurements
found in the SoC datasheet. Note that the TRM refers to the
"normal" drive strength as "standard". If unspecified, the
default will be "normal".
enum:
- "normal"
- "high"
slew-rate:
type: string
description: |
Used to configure the pad's slew rate, which affects the
maximum frequency the pad's output buffer can yield (
"fast" slew rate -> higher pad frequency, "slow" slew rate ->
lower pad frequency). Note that the TRM refers to the "fast"
slew rate as "standard". If unspecified, the default will be
"fast".
enum:
- "fast"
- "slow"