nxp: imx8ulp: enable pinctrl
This commit enables pinctrl on i.MX8ULP. This includes: 1) Adding `pinctrl_soc.h` header file. 2) Adding DTS node for IOMUXC1, which is one of the IPs responsible for managing the 8ULP pads. 3) Adding .dtsi with pin definitions. For now, only the LPUART7 pads are added to this file because this is going to be the only consummer for now. 4) Modifying the `pinctrl_imx.c` driver to work for 8ULP. 5) Enabling the `CONFIG_HAS_MCUX_IOMUXC`, which is a dependency of `CONFIG_PINCTRL_IMX`. Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
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48
dts/bindings/pinctrl/nxp,imx8ulp-pinctrl.yaml
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dts/bindings/pinctrl/nxp,imx8ulp-pinctrl.yaml
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# Copyright 2024 NXP
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# SPDX-License-Identifier: Apache-2.0
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description: Use this compatible for the i.MX8ULP boards
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compatible: "nxp,imx8ulp-pinctrl"
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include: base.yaml
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child-binding:
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description: i.MX8ULP pin controller pin group
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child-binding:
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description: i.MX8ULP pin controller pin configuration node
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include:
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- name: pincfg-node.yaml
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property-allowlist:
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- bias-pull-up
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- bias-pull-down
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- drive-open-drain
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properties:
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pinmux:
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required: true
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type: phandles
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drive-strength:
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type: string
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description: |
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Used to configure the pad's drive strength, which, together
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with the slew rate, affects the maximum frequency the pad's
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output buffer can yield. If "normal" drive strength is used,
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the maximum frequency will be lower as per the measurements
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found in the SoC datasheet. Note that the TRM refers to the
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"normal" drive strength as "standard". If unspecified, the
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default will be "normal".
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enum:
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- "normal"
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- "high"
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slew-rate:
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type: string
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description: |
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Used to configure the pad's slew rate, which affects the
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maximum frequency the pad's output buffer can yield (
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"fast" slew rate -> higher pad frequency, "slow" slew rate ->
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lower pad frequency). Note that the TRM refers to the "fast"
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slew rate as "standard". If unspecified, the default will be
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"fast".
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enum:
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- "fast"
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- "slow"
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