soc: arm: nrf53: add nRF5340 CPUAPP SoC definition
Nordic nRF5340 CPUAPP (Application MCU) SoC definition (Secure and Non-Secure domains). Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
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12 changed files with 309 additions and 1 deletions
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@ -25,7 +25,7 @@ config CPU_HAS_ARM_SAU
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config CPU_HAS_NRF_IDAU
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bool
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depends on SOC_SERIES_NRF91X
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depends on SOC_SERIES_NRF91X || SOC_NRF5340_CPUAPP
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select CPU_HAS_TEE
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help
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MCU implements the nRF (vendor-specific) Security Attribution Unit.
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@ -15,6 +15,9 @@ config HAS_HW_NRF_BPROT
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config HAS_HW_NRF_CC310
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bool
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config HAS_HW_NRF_CC312
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bool
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config HAS_HW_NRF_CCM
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bool
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7
soc/arm/nordic_nrf/nrf53/CMakeLists.txt
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7
soc/arm/nordic_nrf/nrf53/CMakeLists.txt
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@ -0,0 +1,7 @@
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# SPDX-License-Identifier: Apache-2.0
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zephyr_sources(
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soc.c
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)
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zephyr_sources_ifdef(CONFIG_ARM_MPU mpu_regions.c)
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@ -0,0 +1,14 @@
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# Nordic Semiconductor nRF5340 Application MCU
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# Copyright (c) 2019 Nordic Semiconductor ASA
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# SPDX-License-Identifier: Apache-2.0
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if SOC_NRF5340_CPUAPP_QKAA
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config SOC
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default "nRF5340_CPUAPP_QKAA"
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config NUM_IRQS
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default 69
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endif # SOC_NRF5340_CPUAPP_QKAA
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13
soc/arm/nordic_nrf/nrf53/Kconfig.defconfig.series
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13
soc/arm/nordic_nrf/nrf53/Kconfig.defconfig.series
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@ -0,0 +1,13 @@
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# Nordic Semiconductor nRF53 MCU line
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# Copyright (c) 2019 Nordic Semiconductor ASA
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# SPDX-License-Identifier: Apache-2.0
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if SOC_SERIES_NRF53X
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source "soc/arm/nordic_nrf/nrf53/Kconfig.defconfig.nrf53*"
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config SOC_SERIES
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default "nrf53"
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endif # SOC_SERIES_NRF53X
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16
soc/arm/nordic_nrf/nrf53/Kconfig.series
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16
soc/arm/nordic_nrf/nrf53/Kconfig.series
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@ -0,0 +1,16 @@
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# Nordic Semiconductor nRF53 MCU line
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# Copyright (c) 2019 Nordic Semiconductor ASA
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# SPDX-License-Identifier: Apache-2.0
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config SOC_SERIES_NRF53X
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bool "Nordic Semiconductor nRF53 series MCU"
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select CPU_CORTEX_M33
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select CPU_HAS_ARM_MPU
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select SOC_FAMILY_NRF
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select HAS_SYS_POWER_STATE_DEEP_SLEEP_1
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select XIP
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select HAS_NRFX
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select HAS_SEGGER_RTT
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help
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Enable support for NRF53 MCU series
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soc/arm/nordic_nrf/nrf53/Kconfig.soc
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70
soc/arm/nordic_nrf/nrf53/Kconfig.soc
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@ -0,0 +1,70 @@
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# Nordic Semiconductor nRF53 MCU line
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# Copyright (c) 2019 Nordic Semiconductor ASA
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# SPDX-License-Identifier: Apache-2.0
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config SOC_NRF5340_CPUAPP
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depends on SOC_SERIES_NRF53X
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bool
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select CPU_HAS_NRF_IDAU
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select CPU_HAS_FPU
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select ARMV8_M_DSP
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select HAS_HW_NRF_CC312
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select HAS_HW_NRF_CLOCK
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select HAS_HW_NRF_DPPIC
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select HAS_HW_NRF_EGU0
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select HAS_HW_NRF_EGU1
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select HAS_HW_NRF_EGU2
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select HAS_HW_NRF_EGU3
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select HAS_HW_NRF_EGU4
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select HAS_HW_NRF_EGU5
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select HAS_HW_NRF_GPIO0
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select HAS_HW_NRF_GPIO1
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select HAS_HW_NRF_GPIOTE
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select HAS_HW_NRF_I2S
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select HAS_HW_NRF_IPC
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select HAS_HW_NRF_PDM
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select HAS_HW_NRF_POWER
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select HAS_HW_NRF_PWM0
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select HAS_HW_NRF_PWM1
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select HAS_HW_NRF_PWM2
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select HAS_HW_NRF_RTC0
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select HAS_HW_NRF_RTC1
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select HAS_HW_NRF_SAADC
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select HAS_HW_NRF_SPIM0
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select HAS_HW_NRF_SPIM1
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select HAS_HW_NRF_SPIM2
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select HAS_HW_NRF_SPIS0
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select HAS_HW_NRF_SPIS1
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select HAS_HW_NRF_SPU
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select HAS_HW_NRF_TIMER0
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select HAS_HW_NRF_TIMER1
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select HAS_HW_NRF_TIMER2
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select HAS_HW_NRF_TWIM0
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select HAS_HW_NRF_TWIM1
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select HAS_HW_NRF_TWIS0
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select HAS_HW_NRF_TWIS1
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select HAS_HW_NRF_UARTE0
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select HAS_HW_NRF_UARTE1
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select HAS_HW_NRF_WDT
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choice
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prompt "nRF53x MCU Selection"
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depends on SOC_SERIES_NRF53X
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config SOC_NRF5340_CPUAPP_QKAA
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bool "NRF5340_CPUAPP_QKAA"
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select SOC_NRF5340_CPUAPP
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endchoice
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config NRF_ENABLE_CACHE
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bool "Enable cache"
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depends on SOC_NRF5340_CPUAPP && !TRUSTED_EXECUTION_NONSECURE
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default y
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help
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Instruction and Data cache is available on nRF5340 CPUAPP
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(Application MCU). It may only be accessed by Secure code.
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Instruction cache only (I-Cache) is available in nRF5340
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CPUNET (Network MCU).
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42
soc/arm/nordic_nrf/nrf53/dts_fixup.h
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42
soc/arm/nordic_nrf/nrf53/dts_fixup.h
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@ -0,0 +1,42 @@
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/*
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* Copyright (c) 2019 Nordic Semiconductor ASA
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/* SoC level DTS fixup file */
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#define DT_NUM_IRQ_PRIO_BITS \
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DT_ARM_V8M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
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#define DT_NUM_MPU_REGIONS \
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DT_ARM_ARMV8M_MPU_E000ED90_ARM_NUM_MPU_REGIONS
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#define DT_ADC_0_NAME DT_NORDIC_NRF_SAADC_ADC_0_LABEL
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#define DT_UART_0_NAME DT_NORDIC_NRF_UARTE_UART_0_LABEL
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#define DT_UART_1_NAME DT_NORDIC_NRF_UARTE_UART_1_LABEL
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#define DT_FLASH_DEV_NAME \
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DT_NORDIC_NRF53_FLASH_CONTROLLER_FLASH_CONTROLLER_LABEL
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#define DT_GPIO_P0_DEV_NAME DT_NORDIC_NRF_GPIO_GPIO_0_LABEL
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#define DT_GPIO_P1_DEV_NAME DT_NORDIC_NRF_GPIO_GPIO_1_LABEL
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#define DT_I2C_0_NAME DT_NORDIC_NRF_I2C_I2C_0_LABEL
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#define DT_I2C_1_NAME DT_NORDIC_NRF_I2C_I2C_1_LABEL
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#define DT_SPI_0_NAME DT_NORDIC_NRF_SPI_SPI_0_LABEL
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#define DT_SPI_1_NAME DT_NORDIC_NRF_SPI_SPI_1_LABEL
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#define DT_SPI_2_NAME DT_NORDIC_NRF_SPI_SPI_2_LABEL
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#define DT_WDT_0_NAME DT_NORDIC_NRF_WATCHDOG_WDT_0_LABEL
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#define DT_TIMER_0_NAME DT_NORDIC_NRF_TIMER_TIMER_0_LABEL
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#define DT_TIMER_1_NAME DT_NORDIC_NRF_TIMER_TIMER_1_LABEL
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#define DT_TIMER_2_NAME DT_NORDIC_NRF_TIMER_TIMER_2_LABEL
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#define DT_RTC_0_NAME DT_NORDIC_NRF_RTC_RTC_0_LABEL
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#define DT_RTC_1_NAME DT_NORDIC_NRF_RTC_RTC_1_LABEL
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/* End of SoC Level DTS fixup file */
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9
soc/arm/nordic_nrf/nrf53/linker.ld
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9
soc/arm/nordic_nrf/nrf53/linker.ld
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/* linker.ld - Linker command/script file */
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/*
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* Copyright (c) 2014 Wind River Systems, Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <arch/arm/cortex_m/scripts/linker.ld>
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29
soc/arm/nordic_nrf/nrf53/mpu_regions.c
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soc/arm/nordic_nrf/nrf53/mpu_regions.c
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/*
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* Copyright (c) 2017 Linaro Limited.
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* Copyright (c) 2019 Nordic Semiconductor ASA.
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*
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <misc/slist.h>
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#include <arch/arm/cortex_m/mpu/arm_mpu.h>
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static const struct arm_mpu_region mpu_regions[] = {
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/* Region 0 */
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MPU_REGION_ENTRY("FLASH_0",
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CONFIG_FLASH_BASE_ADDRESS,
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REGION_FLASH_ATTR(CONFIG_FLASH_BASE_ADDRESS, \
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CONFIG_FLASH_SIZE * 1024)),
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/* Region 1 */
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MPU_REGION_ENTRY("SRAM_0",
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CONFIG_SRAM_BASE_ADDRESS,
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REGION_RAM_ATTR(CONFIG_SRAM_BASE_ADDRESS, \
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CONFIG_SRAM_SIZE * 1024)),
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};
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const struct arm_mpu_config mpu_config = {
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.num_regions = ARRAY_SIZE(mpu_regions),
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.mpu_regions = mpu_regions,
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};
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78
soc/arm/nordic_nrf/nrf53/soc.c
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78
soc/arm/nordic_nrf/nrf53/soc.c
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/*
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* Copyright (c) 2019 Nordic Semiconductor ASA
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief System/hardware module for Nordic Semiconductor nRF53 family processor
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*
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* This module provides routines to initialize and support board-level hardware
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* for the Nordic Semiconductor nRF53 family processor.
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*/
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#include <kernel.h>
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#include <init.h>
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#include <arch/arm/cortex_m/cmsis.h>
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#include <soc/nrfx_coredep.h>
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#include <logging/log.h>
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#ifdef CONFIG_RUNTIME_NMI
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extern void z_arm_nmi_init(void);
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#define NMI_INIT() z_arm_nmi_init()
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#else
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#define NMI_INIT()
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#endif
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#if defined(CONFIG_SOC_NRF5340_CPUAPP)
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#include <system_nrf5340_application.h>
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#else
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#error "Unknown nRF53 SoC."
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#endif
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#define LOG_LEVEL CONFIG_SOC_LOG_LEVEL
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LOG_MODULE_REGISTER(soc);
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static int nordicsemi_nrf53_init(struct device *arg)
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{
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u32_t key;
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ARG_UNUSED(arg);
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key = irq_lock();
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#ifdef CONFIG_NRF_ENABLE_CACHE
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#ifdef CONFIG_SOC_NRF5340_CPUAPP
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/* Enable the instruction & data cache */
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NRF_CACHE_S->ENABLE = CACHE_ENABLE_ENABLE_Msk;
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#endif /* CONFIG_SOC_NRF5340_CPUAPP */
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#endif
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#if defined(CONFIG_SOC_NRF5340_CPUAPP) && \
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!defined(CONFIG_TRUSTED_EXECUTION_NONSECURE)
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*((u32_t *)0x500046D0) = 0x1;
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#endif
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/* Install default handler that simply resets the CPU
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* if configured in the kernel, NOP otherwise
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*/
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NMI_INIT();
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irq_unlock(key);
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return 0;
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}
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void arch_busy_wait(u32_t time_us)
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{
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nrfx_coredep_delay_us(time_us);
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}
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void z_platform_init(void)
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{
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SystemInit();
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}
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SYS_INIT(nordicsemi_nrf53_init, PRE_KERNEL_1, 0);
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27
soc/arm/nordic_nrf/nrf53/soc.h
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27
soc/arm/nordic_nrf/nrf53/soc.h
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/*
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* Copyright (c) 2019 Nordic Semiconductor ASA
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file SoC configuration macros for the
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* Nordic Semiconductor nRF53 family processors.
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*/
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#ifndef _NORDICSEMI_NRF53_SOC_H_
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#define _NORDICSEMI_NRF53_SOC_H_
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#ifndef _ASMLANGUAGE
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#include <nrfx.h>
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/* Add include for DTS generated information */
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#include <generated_dts_board.h>
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#endif /* !_ASMLANGUAGE */
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#define FLASH_PAGE_ERASE_MAX_TIME_US 89700UL
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#define FLASH_PAGE_MAX_CNT 256UL
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#endif /* _NORDICSEMI_NRF53_SOC_H_ */
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