soc: arm: nrf53: add nRF5340 CPUAPP SoC definition

Nordic nRF5340 CPUAPP (Application MCU) SoC definition
(Secure and Non-Secure domains).

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This commit is contained in:
Ioannis Glaropoulos 2019-08-01 20:47:31 +02:00 committed by Carles Cufí
commit 397d1938de
12 changed files with 309 additions and 1 deletions

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@ -25,7 +25,7 @@ config CPU_HAS_ARM_SAU
config CPU_HAS_NRF_IDAU
bool
depends on SOC_SERIES_NRF91X
depends on SOC_SERIES_NRF91X || SOC_NRF5340_CPUAPP
select CPU_HAS_TEE
help
MCU implements the nRF (vendor-specific) Security Attribution Unit.

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@ -15,6 +15,9 @@ config HAS_HW_NRF_BPROT
config HAS_HW_NRF_CC310
bool
config HAS_HW_NRF_CC312
bool
config HAS_HW_NRF_CCM
bool

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@ -0,0 +1,7 @@
# SPDX-License-Identifier: Apache-2.0
zephyr_sources(
soc.c
)
zephyr_sources_ifdef(CONFIG_ARM_MPU mpu_regions.c)

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@ -0,0 +1,14 @@
# Nordic Semiconductor nRF5340 Application MCU
# Copyright (c) 2019 Nordic Semiconductor ASA
# SPDX-License-Identifier: Apache-2.0
if SOC_NRF5340_CPUAPP_QKAA
config SOC
default "nRF5340_CPUAPP_QKAA"
config NUM_IRQS
default 69
endif # SOC_NRF5340_CPUAPP_QKAA

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@ -0,0 +1,13 @@
# Nordic Semiconductor nRF53 MCU line
# Copyright (c) 2019 Nordic Semiconductor ASA
# SPDX-License-Identifier: Apache-2.0
if SOC_SERIES_NRF53X
source "soc/arm/nordic_nrf/nrf53/Kconfig.defconfig.nrf53*"
config SOC_SERIES
default "nrf53"
endif # SOC_SERIES_NRF53X

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@ -0,0 +1,16 @@
# Nordic Semiconductor nRF53 MCU line
# Copyright (c) 2019 Nordic Semiconductor ASA
# SPDX-License-Identifier: Apache-2.0
config SOC_SERIES_NRF53X
bool "Nordic Semiconductor nRF53 series MCU"
select CPU_CORTEX_M33
select CPU_HAS_ARM_MPU
select SOC_FAMILY_NRF
select HAS_SYS_POWER_STATE_DEEP_SLEEP_1
select XIP
select HAS_NRFX
select HAS_SEGGER_RTT
help
Enable support for NRF53 MCU series

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@ -0,0 +1,70 @@
# Nordic Semiconductor nRF53 MCU line
# Copyright (c) 2019 Nordic Semiconductor ASA
# SPDX-License-Identifier: Apache-2.0
config SOC_NRF5340_CPUAPP
depends on SOC_SERIES_NRF53X
bool
select CPU_HAS_NRF_IDAU
select CPU_HAS_FPU
select ARMV8_M_DSP
select HAS_HW_NRF_CC312
select HAS_HW_NRF_CLOCK
select HAS_HW_NRF_DPPIC
select HAS_HW_NRF_EGU0
select HAS_HW_NRF_EGU1
select HAS_HW_NRF_EGU2
select HAS_HW_NRF_EGU3
select HAS_HW_NRF_EGU4
select HAS_HW_NRF_EGU5
select HAS_HW_NRF_GPIO0
select HAS_HW_NRF_GPIO1
select HAS_HW_NRF_GPIOTE
select HAS_HW_NRF_I2S
select HAS_HW_NRF_IPC
select HAS_HW_NRF_PDM
select HAS_HW_NRF_POWER
select HAS_HW_NRF_PWM0
select HAS_HW_NRF_PWM1
select HAS_HW_NRF_PWM2
select HAS_HW_NRF_RTC0
select HAS_HW_NRF_RTC1
select HAS_HW_NRF_SAADC
select HAS_HW_NRF_SPIM0
select HAS_HW_NRF_SPIM1
select HAS_HW_NRF_SPIM2
select HAS_HW_NRF_SPIS0
select HAS_HW_NRF_SPIS1
select HAS_HW_NRF_SPU
select HAS_HW_NRF_TIMER0
select HAS_HW_NRF_TIMER1
select HAS_HW_NRF_TIMER2
select HAS_HW_NRF_TWIM0
select HAS_HW_NRF_TWIM1
select HAS_HW_NRF_TWIS0
select HAS_HW_NRF_TWIS1
select HAS_HW_NRF_UARTE0
select HAS_HW_NRF_UARTE1
select HAS_HW_NRF_WDT
choice
prompt "nRF53x MCU Selection"
depends on SOC_SERIES_NRF53X
config SOC_NRF5340_CPUAPP_QKAA
bool "NRF5340_CPUAPP_QKAA"
select SOC_NRF5340_CPUAPP
endchoice
config NRF_ENABLE_CACHE
bool "Enable cache"
depends on SOC_NRF5340_CPUAPP && !TRUSTED_EXECUTION_NONSECURE
default y
help
Instruction and Data cache is available on nRF5340 CPUAPP
(Application MCU). It may only be accessed by Secure code.
Instruction cache only (I-Cache) is available in nRF5340
CPUNET (Network MCU).

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@ -0,0 +1,42 @@
/*
* Copyright (c) 2019 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
/* SoC level DTS fixup file */
#define DT_NUM_IRQ_PRIO_BITS \
DT_ARM_V8M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
#define DT_NUM_MPU_REGIONS \
DT_ARM_ARMV8M_MPU_E000ED90_ARM_NUM_MPU_REGIONS
#define DT_ADC_0_NAME DT_NORDIC_NRF_SAADC_ADC_0_LABEL
#define DT_UART_0_NAME DT_NORDIC_NRF_UARTE_UART_0_LABEL
#define DT_UART_1_NAME DT_NORDIC_NRF_UARTE_UART_1_LABEL
#define DT_FLASH_DEV_NAME \
DT_NORDIC_NRF53_FLASH_CONTROLLER_FLASH_CONTROLLER_LABEL
#define DT_GPIO_P0_DEV_NAME DT_NORDIC_NRF_GPIO_GPIO_0_LABEL
#define DT_GPIO_P1_DEV_NAME DT_NORDIC_NRF_GPIO_GPIO_1_LABEL
#define DT_I2C_0_NAME DT_NORDIC_NRF_I2C_I2C_0_LABEL
#define DT_I2C_1_NAME DT_NORDIC_NRF_I2C_I2C_1_LABEL
#define DT_SPI_0_NAME DT_NORDIC_NRF_SPI_SPI_0_LABEL
#define DT_SPI_1_NAME DT_NORDIC_NRF_SPI_SPI_1_LABEL
#define DT_SPI_2_NAME DT_NORDIC_NRF_SPI_SPI_2_LABEL
#define DT_WDT_0_NAME DT_NORDIC_NRF_WATCHDOG_WDT_0_LABEL
#define DT_TIMER_0_NAME DT_NORDIC_NRF_TIMER_TIMER_0_LABEL
#define DT_TIMER_1_NAME DT_NORDIC_NRF_TIMER_TIMER_1_LABEL
#define DT_TIMER_2_NAME DT_NORDIC_NRF_TIMER_TIMER_2_LABEL
#define DT_RTC_0_NAME DT_NORDIC_NRF_RTC_RTC_0_LABEL
#define DT_RTC_1_NAME DT_NORDIC_NRF_RTC_RTC_1_LABEL
/* End of SoC Level DTS fixup file */

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@ -0,0 +1,9 @@
/* linker.ld - Linker command/script file */
/*
* Copyright (c) 2014 Wind River Systems, Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <arch/arm/cortex_m/scripts/linker.ld>

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@ -0,0 +1,29 @@
/*
* Copyright (c) 2017 Linaro Limited.
* Copyright (c) 2019 Nordic Semiconductor ASA.
*
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <misc/slist.h>
#include <arch/arm/cortex_m/mpu/arm_mpu.h>
static const struct arm_mpu_region mpu_regions[] = {
/* Region 0 */
MPU_REGION_ENTRY("FLASH_0",
CONFIG_FLASH_BASE_ADDRESS,
REGION_FLASH_ATTR(CONFIG_FLASH_BASE_ADDRESS, \
CONFIG_FLASH_SIZE * 1024)),
/* Region 1 */
MPU_REGION_ENTRY("SRAM_0",
CONFIG_SRAM_BASE_ADDRESS,
REGION_RAM_ATTR(CONFIG_SRAM_BASE_ADDRESS, \
CONFIG_SRAM_SIZE * 1024)),
};
const struct arm_mpu_config mpu_config = {
.num_regions = ARRAY_SIZE(mpu_regions),
.mpu_regions = mpu_regions,
};

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@ -0,0 +1,78 @@
/*
* Copyright (c) 2019 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief System/hardware module for Nordic Semiconductor nRF53 family processor
*
* This module provides routines to initialize and support board-level hardware
* for the Nordic Semiconductor nRF53 family processor.
*/
#include <kernel.h>
#include <init.h>
#include <arch/arm/cortex_m/cmsis.h>
#include <soc/nrfx_coredep.h>
#include <logging/log.h>
#ifdef CONFIG_RUNTIME_NMI
extern void z_arm_nmi_init(void);
#define NMI_INIT() z_arm_nmi_init()
#else
#define NMI_INIT()
#endif
#if defined(CONFIG_SOC_NRF5340_CPUAPP)
#include <system_nrf5340_application.h>
#else
#error "Unknown nRF53 SoC."
#endif
#define LOG_LEVEL CONFIG_SOC_LOG_LEVEL
LOG_MODULE_REGISTER(soc);
static int nordicsemi_nrf53_init(struct device *arg)
{
u32_t key;
ARG_UNUSED(arg);
key = irq_lock();
#ifdef CONFIG_NRF_ENABLE_CACHE
#ifdef CONFIG_SOC_NRF5340_CPUAPP
/* Enable the instruction & data cache */
NRF_CACHE_S->ENABLE = CACHE_ENABLE_ENABLE_Msk;
#endif /* CONFIG_SOC_NRF5340_CPUAPP */
#endif
#if defined(CONFIG_SOC_NRF5340_CPUAPP) && \
!defined(CONFIG_TRUSTED_EXECUTION_NONSECURE)
*((u32_t *)0x500046D0) = 0x1;
#endif
/* Install default handler that simply resets the CPU
* if configured in the kernel, NOP otherwise
*/
NMI_INIT();
irq_unlock(key);
return 0;
}
void arch_busy_wait(u32_t time_us)
{
nrfx_coredep_delay_us(time_us);
}
void z_platform_init(void)
{
SystemInit();
}
SYS_INIT(nordicsemi_nrf53_init, PRE_KERNEL_1, 0);

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@ -0,0 +1,27 @@
/*
* Copyright (c) 2019 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file SoC configuration macros for the
* Nordic Semiconductor nRF53 family processors.
*/
#ifndef _NORDICSEMI_NRF53_SOC_H_
#define _NORDICSEMI_NRF53_SOC_H_
#ifndef _ASMLANGUAGE
#include <nrfx.h>
/* Add include for DTS generated information */
#include <generated_dts_board.h>
#endif /* !_ASMLANGUAGE */
#define FLASH_PAGE_ERASE_MAX_TIME_US 89700UL
#define FLASH_PAGE_MAX_CNT 256UL
#endif /* _NORDICSEMI_NRF53_SOC_H_ */