From 397c48a13e92cac8daaa7d1cd463b60e401eb13b Mon Sep 17 00:00:00 2001 From: TOKITA Hiroshi Date: Wed, 7 Aug 2024 20:01:52 +0900 Subject: [PATCH] dts: arm: renesas: ra4: Use renesas,ra-pinctrl-pfs driver Switch the pinctrl driver to renesas,ra-pinctrl-pfs which can be used with FSP. Signed-off-by: TOKITA Hiroshi --- drivers/gpio/gpio_renesas_ra.c | 26 ++++++++++++------------- drivers/pinctrl/renesas/ra/pinctrl_ra.c | 13 +++++++++++++ dts/arm/renesas/ra/ra-cm4-common.dtsi | 2 +- soc/renesas/ra/common_fsp/pinctrl_soc.h | 4 ++++ 4 files changed, 31 insertions(+), 14 deletions(-) diff --git a/drivers/gpio/gpio_renesas_ra.c b/drivers/gpio/gpio_renesas_ra.c index 9f4fe59c83b..8da6f593e66 100644 --- a/drivers/gpio/gpio_renesas_ra.c +++ b/drivers/gpio/gpio_renesas_ra.c @@ -144,7 +144,7 @@ static int gpio_ra_pin_configure(const struct device *dev, gpio_pin_t pin, gpio_ const enum gpio_int_trig trig = flags & (GPIO_INT_LOW_0 | GPIO_INT_HIGH_1); const struct gpio_ra_config *config = dev->config; struct gpio_ra_data *data = dev->data; - struct pinctrl_ra_pin pincfg = {0}; + struct ra_pinctrl_soc_pin pincfg = {0}; if ((flags & GPIO_OUTPUT) && (flags & GPIO_INPUT)) { /* Pin cannot be configured as input and output */ @@ -155,25 +155,25 @@ static int gpio_ra_pin_configure(const struct device *dev, gpio_pin_t pin, gpio_ } if (flags & GPIO_OUTPUT) { - pincfg.config |= BIT(PmnPFS_PDR_POS); + pincfg.cfg |= BIT(R_PFS_PORT_PIN_PmnPFS_PDR_Pos); } if (flags & GPIO_PULL_UP) { - pincfg.config |= BIT(PmnPFS_PCR_POS); + pincfg.cfg |= BIT(R_PFS_PORT_PIN_PmnPFS_PCR_Pos); } if ((flags & GPIO_SINGLE_ENDED) && (flags & GPIO_LINE_OPEN_DRAIN)) { - pincfg.config |= BIT(PmnPFS_NCODR_POS); + pincfg.cfg |= BIT(R_PFS_PORT_PIN_PmnPFS_NCODR_Pos); } if (flags & GPIO_INT_ENABLE) { - pincfg.config |= BIT(PmnPFS_ISEL_POS); + pincfg.cfg |= BIT(R_PFS_PORT_PIN_PmnPFS_ISEL_Pos); } - pincfg.config &= ~BIT(PmnPFS_PMR_POS); + pincfg.cfg &= ~BIT(R_PFS_PORT_PIN_PmnPFS_PMR_Pos); - pincfg.pin = pin; - pincfg.port = config->port; + pincfg.pin_num = pin; + pincfg.port_num = config->port; if (flags & GPIO_INT_ENABLE) { const struct gpio_ra_irq_info *irq_info; @@ -230,7 +230,7 @@ static int gpio_ra_pin_get_config(const struct device *dev, gpio_pin_t pin, gpio { const struct gpio_ra_config *config = dev->config; const struct gpio_ra_irq_info *irq_info; - struct pinctrl_ra_pin pincfg; + struct ra_pinctrl_soc_pin pincfg; ra_isr_handler cb; const void *cbarg; uint32_t intcfg; @@ -239,22 +239,22 @@ static int gpio_ra_pin_get_config(const struct device *dev, gpio_pin_t pin, gpio memset(flags, 0, sizeof(gpio_flags_t)); - err = pinctrl_ra_query_config(config->port, pin, &pincfg); + err = ra_pinctrl_query_config(config->port, pin, &pincfg); if (err < 0) { return err; } - if (pincfg.config & BIT(PmnPFS_PDR_POS)) { + if (pincfg.cfg & BIT(R_PFS_PORT_PIN_PmnPFS_PDR_Pos)) { *flags |= GPIO_OUTPUT; } else { *flags |= GPIO_INPUT; } - if (pincfg.config & BIT(PmnPFS_ISEL_POS)) { + if (pincfg.cfg & BIT(R_PFS_PORT_PIN_PmnPFS_ISEL_Pos)) { *flags |= GPIO_INT_ENABLE; } - if (pincfg.config & BIT(PmnPFS_PCR_POS)) { + if (pincfg.cfg & BIT(R_PFS_PORT_PIN_PmnPFS_PCR_Pos)) { *flags |= GPIO_PULL_UP; } diff --git a/drivers/pinctrl/renesas/ra/pinctrl_ra.c b/drivers/pinctrl/renesas/ra/pinctrl_ra.c index efaac2f34f7..0f2bc85bd60 100644 --- a/drivers/pinctrl/renesas/ra/pinctrl_ra.c +++ b/drivers/pinctrl/renesas/ra/pinctrl_ra.c @@ -26,3 +26,16 @@ int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, uintp return 0; } + +int ra_pinctrl_query_config(uint32_t port, uint32_t pin, pinctrl_soc_pin_t *pincfg) +{ + if (port >= RA_PINCTRL_PORT_NUM || pin >= RA_PINCTRL_PIN_NUM) { + return -EINVAL; + } + + pincfg->port_num = port; + pincfg->pin_num = pin; + + pincfg->cfg = R_PFS->PORT[port].PIN[pin].PmnPFS; + return 0; +} diff --git a/dts/arm/renesas/ra/ra-cm4-common.dtsi b/dts/arm/renesas/ra/ra-cm4-common.dtsi index 4ef18141e6c..88fe55932b0 100644 --- a/dts/arm/renesas/ra/ra-cm4-common.dtsi +++ b/dts/arm/renesas/ra/ra-cm4-common.dtsi @@ -240,7 +240,7 @@ }; pinctrl: pinctrl@40040800 { - compatible = "renesas,ra-pinctrl"; + compatible = "renesas,ra-pinctrl-pfs"; reg = <0x40040800 0x500 0x40040d03 0x1>; reg-names = "pfs", "pmisc_pwpr"; status = "okay"; diff --git a/soc/renesas/ra/common_fsp/pinctrl_soc.h b/soc/renesas/ra/common_fsp/pinctrl_soc.h index 0df9ec39111..dc08dc3db10 100644 --- a/soc/renesas/ra/common_fsp/pinctrl_soc.h +++ b/soc/renesas/ra/common_fsp/pinctrl_soc.h @@ -12,6 +12,8 @@ #include +#define RA_PINCTRL_PORT_NUM ARRAY_SIZE(((R_PFS_Type *)0)->PORT) +#define RA_PINCTRL_PIN_NUM ARRAY_SIZE(((R_PFS_PORT_Type *)0)->PIN) /** * @brief Type to hold a renesas ra pin's pinctrl configuration. */ @@ -26,6 +28,8 @@ struct ra_pinctrl_soc_pin { typedef struct ra_pinctrl_soc_pin pinctrl_soc_pin_t; +int ra_pinctrl_query_config(uint32_t port, uint32_t pin, pinctrl_soc_pin_t *pincfg); + /** * @brief Utility macro to initialize each pin. *